3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
20 (update: actually this is being added now:
21 https://bugs.libre-soc.org/show_bug.cgi?id=737)
24 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
26 from nmigen
.cli
import rtlil
28 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
29 from openpower
.decoder
.power_regspec_map
import regspec_decode
30 from openpower
.sv
.svp64
import SVP64Rec
32 from nmutil
.picker
import PriorityPicker
33 from nmutil
.util
import treereduce
34 from nmutil
.singlepipe
import ControlBase
36 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
37 from soc
.regfile
.regfiles
import RegFiles
38 from openpower
.decoder
.power_decoder2
import get_rdflags
39 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from openpower
.decoder
.power_enums
import MicrOp
, Function
42 from soc
.simple
.core_data
import CoreInput
, CoreOutput
44 from collections
import defaultdict
, namedtuple
47 from nmutil
.util
import rising_edge
49 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
50 ByRegSpec
= namedtuple("ByRegSpec", ["okflag", "regport", "wid", "specs"])
52 # helper function for reducing a list of signals down to a parallel
54 def ortreereduce(tree
, attr
="o_data"):
55 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
58 def ortreereduce_sig(tree
):
59 return treereduce(tree
, operator
.or_
, lambda x
: x
)
62 # helper function to place full regs declarations first
63 def sort_fuspecs(fuspecs
):
65 for (regname
, fspec
) in fuspecs
.items():
66 if regname
.startswith("full"):
67 res
.append((regname
, fspec
))
68 for (regname
, fspec
) in fuspecs
.items():
69 if not regname
.startswith("full"):
70 res
.append((regname
, fspec
))
71 return res
# enumerate(res)
74 # a hazard bitvector "remap" function which returns an AST expression
75 # that remaps read/write hazard regfile port numbers to either a full
76 # bitvector or a reduced subset one. SPR for example is reduced to a
78 # CRITICALLY-IMPORTANT NOTE: these bitvectors *have* to match up per
79 # regfile! therefore the remapping is per regfile, *NOT* per regfile
80 # port and certainly not based on whether it is a read port or write port.
81 # note that any reductions here will result in degraded performance due
82 # to conflicts, but at least it keeps the hazard matrix sizes down to "sane"
83 def bitvector_remap(regfile
, rfile
, port
):
84 # 8-bits (at the moment, no SVP64), CR is unary: no remap
87 # 3 bits, unary alrady: return the port
90 # 3 bits, unary: return the port
93 # 3 bits, unary: return the port
94 if regfile
== 'SVSTATE':
96 # 9 bits (9 entries), might be unary already
98 if rfile
.unary
: # FAST might be unary already
102 # 10 bits (!!) - reduce to one
104 if rfile
.unary
: # FAST might be unary already
109 if rfile
.unary
: # INT, check if unary/binary
115 # derive from ControlBase rather than have a separate Stage instance,
116 # this is simpler to do
117 class NonProductionCore(ControlBase
):
118 def __init__(self
, pspec
):
121 # test is SVP64 is to be enabled
122 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
124 # test to see if regfile ports should be reduced
125 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
126 (pspec
.regreduce
== True))
128 # test to see if overlapping of instructions is allowed
129 # (not normally enabled for TestIssuer FSM but useful for checking
130 # the bitvector hazard detection, before doing In-Order)
131 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
132 (pspec
.allow_overlap
== True))
135 self
.make_hazard_vecs
= self
.allow_overlap
136 self
.core_type
= "fsm"
137 if hasattr(pspec
, "core_type"):
138 self
.core_type
= pspec
.core_type
140 super().__init
__(stage
=self
)
142 # single LD/ST funnel for memory access
143 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
146 # function units (only one each)
147 # only include mmu if enabled in pspec
148 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
150 # link LoadStore1 into MMU
151 mmu
= self
.fus
.get_fu('mmu0')
152 ldst0
= self
.fus
.get_fu('ldst0')
153 print ("core pspec", pspec
.ldst_ifacetype
)
154 print ("core mmu", mmu
)
156 lsi
= l0
.cmpi
.lsmem
.lsi
# a LoadStore1 Interface object
157 print ("core lsmem.lsi", lsi
)
158 mmu
.alu
.set_ldst_interface(lsi
)
159 # urr store I-Cache in core so it is easier to get at
160 self
.icache
= lsi
.icache
162 # register files (yes plural)
163 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
165 # set up input and output: unusual requirement to set data directly
166 # (due to the way that the core is set up in a different domain,
167 # see TestIssuer.setup_peripherals
168 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
169 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
171 # actual internal input data used (captured)
172 self
.ireg
= self
.ispec()
174 # create per-FU instruction decoders (subsetted). these "satellite"
175 # decoders reduce wire fan-out from the one (main) PowerDecoder2
176 # (used directly by the trap unit) to the *twelve* (or more)
177 # Function Units. we can either have 32 wires (the instruction)
178 # to each, or we can have well over a 200 wire fan-out (to 12
179 # ALUs). it's an easy choice to make.
183 # eep, these should be *per FU* i.e. for FunctionUnitBaseMulti
184 # they should be shared (put into the ALU *once*).
186 for funame
, fu
in self
.fus
.fus
.items():
187 f_name
= fu
.fnunit
.name
188 fnunit
= fu
.fnunit
.value
189 opkls
= fu
.opsubsetkls
191 # TRAP decoder is the *main* decoder
192 self
.trapunit
= funame
194 assert funame
not in self
.decoders
195 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
197 state
=self
.ireg
.state
,
198 svp64_en
=self
.svp64_en
,
199 regreduce_en
=self
.regreduce_en
)
200 self
.des
[funame
] = self
.decoders
[funame
].do
201 print ("create decoder subset", funame
, opkls
, self
.des
[funame
])
203 # create per-Function Unit write-after-write hazard signals
204 # yes, really, this should have been added in ReservationStations
206 for funame
, fu
in self
.fus
.fus
.items():
207 fu
._waw
_hazard
= Signal(name
="waw_%s" % funame
)
209 # share the SPR decoder with the MMU if it exists
210 if "mmu0" in self
.decoders
:
211 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
213 # next 3 functions are Stage API Compliance
214 def setup(self
, m
, i
):
218 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
223 # elaborate function to create HDL
224 def elaborate(self
, platform
):
225 m
= super().elaborate(platform
)
227 # for testing purposes, to cut down on build time in coriolis2
228 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
229 x
= Signal() # dummy signal
234 m
.submodules
.fus
= self
.fus
235 m
.submodules
.l0
= l0
= self
.l0
236 self
.regs
.elaborate_into(m
, platform
)
240 # amalgamate write-hazards into a single top-level Signal
241 self
.waw_hazard
= Signal()
243 for funame
, fu
in self
.fus
.fus
.items():
244 whaz
.append(fu
._waw
_hazard
)
245 comb
+= self
.waw_hazard
.eq(Cat(*whaz
).bool())
248 self
.connect_satellite_decoders(m
)
250 # ssh, cheat: trap uses the main decoder because of the rewriting
251 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
253 # connect up Function Units, then read/write ports, and hazard conflict
254 self
.issue_conflict
= Signal()
255 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
256 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
257 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
258 if self
.allow_overlap
:
259 comb
+= self
.issue_conflict
.eq(raw_hazard
)
261 # note if an exception happened. in a pipelined or OoO design
262 # this needs to be accompanied by "shadowing" (or stalling)
264 for exc
in self
.fus
.excs
.values():
265 el
.append(exc
.happened
)
266 if len(el
) > 0: # at least one exception
267 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
271 def connect_satellite_decoders(self
, m
):
273 for k
, v
in self
.decoders
.items():
274 # connect each satellite decoder and give it the instruction.
275 # as subset decoders this massively reduces wire fanout given
276 # the large number of ALUs
277 m
.submodules
["dec_%s" % k
] = v
278 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
279 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
280 # sigh due to SVP64 RA_OR_ZERO detection connect these too
281 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
282 if not self
.svp64_en
:
284 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
285 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
286 if k
== self
.trapunit
:
288 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
289 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
290 # only the LDST PowerDecodeSubset *actually* needs to
291 # know to use the alternative decoder. this is all
293 if not k
.lower().startswith("ldst"):
295 comb
+= v
.use_svp64_ldst_dec
.eq( self
.ireg
.use_svp64_ldst_dec
)
297 def connect_instruction(self
, m
):
298 """connect_instruction
300 uses decoded (from PowerOp) function unit information from CSV files
301 to ascertain which Function Unit should deal with the current
304 some (such as OP_ATTN, OP_NOP) are dealt with here, including
305 ignoring it and halting the processor. OP_NOP is a bit annoying
306 because the issuer expects busy flag still to be raised then lowered.
307 (this requires a fake counter to be set).
309 comb
, sync
= m
.d
.comb
, m
.d
.sync
312 # indicate if core is busy
313 busy_o
= self
.o
.busy_o
314 any_busy_o
= self
.o
.any_busy_o
316 # connect up temporary copy of incoming instruction. the FSM will
317 # either blat the incoming instruction (if valid) into self.ireg
318 # or if the instruction could not be delivered, keep dropping the
319 # latched copy into ireg
320 ilatch
= self
.ispec()
321 self
.instr_active
= Signal()
323 # enable/busy-signals for each FU, get one bit for each FU (by name)
324 fu_enable
= Signal(len(fus
), reset_less
=True)
325 fu_busy
= Signal(len(fus
), reset_less
=True)
328 for i
, funame
in enumerate(fus
.keys()):
329 fu_bitdict
[funame
] = fu_enable
[i
]
330 fu_selected
[funame
] = fu_busy
[i
]
332 # identify function units and create a list by fnunit so that
333 # PriorityPickers can be created for selecting one of them that
334 # isn't busy at the time the incoming instruction needs passing on
335 by_fnunit
= defaultdict(list)
336 for fname
, member
in Function
.__members
__.items():
337 for funame
, fu
in fus
.items():
338 fnunit
= fu
.fnunit
.value
339 if member
.value
& fnunit
: # this FU handles this type of op
340 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
342 # ok now just print out the list of FUs by Function, because we can
343 for fname
, fu_list
in by_fnunit
.items():
344 print ("FUs by type", fname
, fu_list
)
346 # now create a PriorityPicker per FU-type such that only one
347 # non-busy FU will be picked
349 fu_found
= Signal() # take a note if no Function Unit was available
350 for fname
, fu_list
in by_fnunit
.items():
351 i_pp
= PriorityPicker(len(fu_list
))
352 m
.submodules
['i_pp_%s' % fname
] = i_pp
354 for i
, (funame
, fu
) in enumerate(fu_list
):
355 # match the decoded instruction (e.do.fn_unit) against the
356 # "capability" of this FU, gate that by whether that FU is
357 # busy, and drop that into the PriorityPicker.
358 # this will give us an output of the first available *non-busy*
359 # Function Unit (Reservation Statio) capable of handling this
361 fnunit
= fu
.fnunit
.value
362 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
363 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
364 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
366 i_l
.append(en_req
) # store in list for doing the Cat-trick
367 # picker output, gated by enable: store in fu_bitdict
368 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
369 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
370 comb
+= fu_bitdict
[funame
].eq(po
)
371 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
372 # if we don't do this, then when there are no FUs available,
373 # the "p.o_ready" signal will go back "ok we accepted this
374 # instruction" which of course isn't true.
375 with m
.If(i_pp
.en_o
):
376 comb
+= fu_found
.eq(1)
377 # for each input, Cat them together and drop them into the picker
378 comb
+= i_pp
.i
.eq(Cat(*i_l
))
380 # rdmask, which is for registers needs to come from the *main* decoder
381 for funame
, fu
in fus
.items():
382 rdmask
= get_rdflags(m
, self
.ireg
.e
, fu
)
383 comb
+= fu
.rdmaskn
.eq(~rdmask
)
385 # sigh - need a NOP counter
387 with m
.If(counter
!= 0):
388 sync
+= counter
.eq(counter
- 1)
391 # default to reading from incoming instruction: may be overridden
392 # by copy from latch when "waiting"
393 comb
+= self
.ireg
.eq(self
.i
)
394 # always say "ready" except if overridden
395 comb
+= self
.p
.o_ready
.eq(1)
398 with m
.State("READY"):
399 with m
.If(self
.p
.i_valid
): # run only when valid
400 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
401 # check for ATTN: halt if true
402 with m
.Case(MicrOp
.OP_ATTN
):
403 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
405 # fake NOP - this isn't really used (Issuer detects NOP)
406 with m
.Case(MicrOp
.OP_NOP
):
407 sync
+= counter
.eq(2)
411 comb
+= self
.instr_active
.eq(1)
412 comb
+= self
.p
.o_ready
.eq(0)
413 # connect instructions. only one enabled at a time
414 for funame
, fu
in fus
.items():
415 do
= self
.des
[funame
]
416 enable
= fu_bitdict
[funame
]
418 # run this FunctionUnit if enabled route op,
419 # issue, busy, read flags and mask to FU
421 # operand comes from the *local* decoder
422 # do not actually issue, though, if there
423 # is a waw hazard. decoder has to still
424 # be asserted in order to detect that, tho
425 comb
+= fu
.oper_i
.eq_from(do
)
427 # URRR this is truly dreadful.
428 # OP_FETCH_FAILED is a "fake" op.
429 # no instruction creates it. OP_TRAP
430 # uses the *main* decoder: this is
431 # a *Satellite* decoder that reacts
432 # on *insn_in*... not fake ops. gaah.
433 main_op
= self
.ireg
.e
.do
434 with m
.If(main_op
.insn_type
==
435 MicrOp
.OP_FETCH_FAILED
):
436 comb
+= fu
.oper_i
.insn_type
.eq(
437 MicrOp
.OP_FETCH_FAILED
)
438 comb
+= fu
.oper_i
.fn_unit
.eq(
440 # issue when valid (and no write-hazard)
441 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
442 # instruction ok, indicate ready
443 comb
+= self
.p
.o_ready
.eq(1)
445 if self
.allow_overlap
:
446 with m
.If(~fu_found | self
.waw_hazard
):
447 # latch copy of instruction
448 sync
+= ilatch
.eq(self
.i
)
449 comb
+= self
.p
.o_ready
.eq(1) # accept
453 with m
.State("WAITING"):
454 comb
+= self
.instr_active
.eq(1)
455 comb
+= self
.p
.o_ready
.eq(0)
457 # using copy of instruction, keep waiting until an FU is free
458 comb
+= self
.ireg
.eq(ilatch
)
459 with m
.If(fu_found
): # wait for conflict to clear
460 # connect instructions. only one enabled at a time
461 for funame
, fu
in fus
.items():
462 do
= self
.des
[funame
]
463 enable
= fu_bitdict
[funame
]
465 # run this FunctionUnit if enabled route op,
466 # issue, busy, read flags and mask to FU
468 # operand comes from the *local* decoder,
469 # which is asserted even if not issued,
470 # so that WaW-detection can check for hazards.
471 # only if the waw hazard is clear does the
472 # instruction actually get issued
473 comb
+= fu
.oper_i
.eq_from(do
)
475 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
476 with m
.If(~self
.waw_hazard
):
477 comb
+= self
.p
.o_ready
.eq(1)
481 print ("core: overlap allowed", self
.allow_overlap
)
482 # true when any FU is busy (including the cycle where it is perhaps
483 # to be issued - because that's what fu_busy is)
484 comb
+= any_busy_o
.eq(fu_busy
.bool())
485 if not self
.allow_overlap
:
486 # for simple non-overlap, if any instruction is busy, set
487 # busy output for core.
488 comb
+= busy_o
.eq(any_busy_o
)
490 # sigh deal with a fun situation that needs to be investigated
492 with m
.If(self
.issue_conflict
):
494 # make sure that LDST, SPR, MMU, Branch and Trap all say "busy"
495 # and do not allow overlap. these are all the ones that
496 # are non-forward-progressing: exceptions etc. that otherwise
497 # change CoreState for some reason (MSR, PC, SVSTATE)
498 for funame
, fu
in fus
.items():
499 if (funame
.lower().startswith('ldst') or
500 funame
.lower().startswith('branch') or
501 funame
.lower().startswith('mmu') or
502 funame
.lower().startswith('spr') or
503 funame
.lower().startswith('trap')):
504 with m
.If(fu
.busy_o
):
507 # return both the function unit "enable" dict as well as the "busy".
508 # the "busy-or-issued" can be passed in to the Read/Write port
509 # connecters to give them permission to request access to regfiles
510 return fu_bitdict
, fu_selected
512 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
513 rdpickers
, regfile
, regname
, fspec
):
514 comb
, sync
= m
.d
.comb
, m
.d
.sync
520 # select the required read port. these are pre-defined sizes
521 rfile
= regs
.rf
[regfile
.lower()]
522 rport
= rfile
.r_ports
[rpidx
]
523 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
526 # for checking if the read port has an outstanding write
527 if self
.make_hazard_vecs
:
528 wv
= regs
.wv
[regfile
.lower()]
529 wvchk
= wv
.q_int
# write-vec bit-level hazard check
531 # if a hazard is detected on this read port, simply blithely block
532 # every FU from reading on it. this is complete overkill but very
534 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
537 if not isinstance(fspecs
, list):
543 for i
, fspec
in enumerate(fspecs
):
544 # get the regfile specs for this regfile port
545 print ("fpsec", i
, fspec
, len(fspec
.specs
))
546 name
= "%s_%s_%d" % (regfile
, regname
, i
)
547 ppoffs
.append(pplen
) # record offset for picker
548 pplen
+= len(fspec
.specs
)
549 rdflag
= Signal(name
="rdflag_"+name
, reset_less
=True)
550 comb
+= rdflag
.eq(fspec
.okflag
)
551 rdflags
.append(rdflag
)
553 print ("pplen", pplen
)
555 # create a priority picker to manage this port
556 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
557 m
.submodules
["rdpick_%s_%s" % (regfile
, rpidx
)] = rdpick
563 for i
, fspec
in enumerate(fspecs
):
564 (rf
, _read
, wid
, fuspecs
) = \
565 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
566 # connect up the FU req/go signals, and the reg-read to the FU
567 # and create a Read Broadcast Bus
568 for pi
, fuspec
in enumerate(fspec
.specs
):
569 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
571 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
572 fu_active
= fu_selected
[funame
]
573 fu_issued
= fu_bitdict
[funame
]
575 # get (or set up) a latched copy of read register number
576 # and (sigh) also the read-ok flag
577 # TODO: use nmutil latchregister
578 rhname
= "%s_%s_%d" % (regfile
, regname
, i
)
579 rdflag
= Signal(name
="rdflag_%s_%s" % (funame
, rhname
),
581 if rhname
not in fu
.rf_latches
:
582 rfl
= Signal(name
="rdflag_latch_%s_%s" % (funame
, rhname
))
583 fu
.rf_latches
[rhname
] = rfl
584 with m
.If(fu
.issue_i
):
585 sync
+= rfl
.eq(rdflags
[i
])
587 rfl
= fu
.rf_latches
[rhname
]
589 # now the register port
590 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
591 read
= Signal
.like(_read
, name
="read_"+rname
)
592 if rname
not in fu
.rd_latches
:
593 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
594 fu
.rd_latches
[rname
] = rdl
595 with m
.If(fu
.issue_i
):
596 sync
+= rdl
.eq(_read
)
598 rdl
= fu
.rd_latches
[rname
]
600 # make the read immediately available on issue cycle
601 # after the read cycle, otherwies use the latched copy.
602 # this captures the regport and okflag on issue
603 with m
.If(fu
.issue_i
):
604 comb
+= read
.eq(_read
)
605 comb
+= rdflag
.eq(rdflags
[i
])
608 comb
+= rdflag
.eq(rfl
)
610 # connect request-read to picker input, and output to go-rd
611 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
612 pick
= Signal(name
="pick_"+name
) # picker input
613 rp
= Signal(name
="rp_"+name
) # picker output
614 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
615 rhazard
= Signal(name
="rhaz_"+name
)
617 # exclude any currently-enabled read-request (mask out active)
618 # entirely block anything hazarded from being picked
619 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflag
&
620 ~delay_pick
& ~rhazard
)
621 comb
+= rdpick
.i
[pi
].eq(pick
)
622 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
624 # if picked, select read-port "reg select" number to port
625 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
626 sync
+= delay_pick
.eq(rp
) # delayed "pick"
627 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
629 # the read-enable happens combinatorially (see mux-bus below)
630 # but it results in the data coming out on a one-cycle delay.
634 addrs
.append(addr_en
)
637 # use the *delayed* pick signal to put requested data onto bus
638 with m
.If(delay_pick
):
639 # connect regfile port to input, creating fan-out Bus
641 print("reg connect widths",
642 regfile
, regname
, pi
, funame
,
643 src
.shape(), rport
.o_data
.shape())
644 # all FUs connect to same port
645 comb
+= src
.eq(rport
.o_data
)
647 if not self
.make_hazard_vecs
:
650 # read the write-hazard bitvector (wv) for any bit that is
651 wvchk_en
= Signal(len(wvchk
), name
="wv_chk_addr_en_"+name
)
652 issue_active
= Signal(name
="rd_iactive_"+name
)
653 # XXX combinatorial loop here
654 comb
+= issue_active
.eq(fu_active
& rdflag
)
655 with m
.If(issue_active
):
657 comb
+= wvchk_en
.eq(read
)
659 comb
+= wvchk_en
.eq(1<<read
)
660 # if FU is busy (which doesn't get set at the same time as
661 # issue) and no hazard was detected, clear wvchk_en (i.e.
662 # stop checking for hazards). there is a loop here, but it's
663 # via a DFF, so is ok. some linters may complain, but hey.
664 with m
.If(fu
.busy_o
& ~rhazard
):
665 comb
+= wvchk_en
.eq(0)
667 # read-hazard is ANDed with (filtered by) what is actually
669 comb
+= rhazard
.eq((wvchk
& wvchk_en
).bool())
671 wvens
.append(wvchk_en
)
673 # or-reduce the muxed read signals
675 # for unary-addressed
676 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
678 # for binary-addressed
679 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
680 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
681 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
683 if not self
.make_hazard_vecs
:
684 return Const(0) # declare "no hazards"
686 # enable the read bitvectors for this issued instruction
687 # and return whether any write-hazard bit is set
688 wvchk_and
= Signal(len(wvchk
), name
="wv_chk_"+name
)
689 comb
+= wvchk_and
.eq(wvchk
& ortreereduce_sig(wvens
))
690 comb
+= hazard_detected
.eq(wvchk_and
.bool())
691 return hazard_detected
693 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
694 """connect read ports
696 orders the read regspecs into a dict-of-dicts, by regfile, by
697 regport name, then connects all FUs that want that regport by
698 way of a PriorityPicker.
700 comb
, sync
= m
.d
.comb
, m
.d
.sync
705 # dictionary of lists of regfile read ports
706 byregfiles_rdspec
= self
.get_byregfiles(m
, True)
708 # okaay, now we need a PriorityPicker per regfile per regfile port
709 # loootta pickers... peter piper picked a pack of pickled peppers...
711 for regfile
, fuspecs
in byregfiles_rdspec
.items():
712 rdpickers
[regfile
] = {}
714 # argh. an experiment to merge RA and RB in the INT regfile
715 # (we have too many read/write ports)
716 if self
.regreduce_en
:
718 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
719 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
720 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
721 if regfile
== 'FAST':
722 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
723 if 'fast2' in fuspecs
:
724 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
725 if 'fast3' in fuspecs
:
726 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
728 # for each named regfile port, connect up all FUs to that port
729 # also return (and collate) hazard detection)
730 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
731 print("connect rd", regname
, fspec
)
732 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
737 return Cat(*rd_hazard
).bool()
739 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
740 funame
, regname
, idx
,
741 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
743 """make_hazards: a setter and a clearer for the regfile write ports
745 setter is at issue time (using PowerDecoder2 regfile write numbers)
746 clearer is at regfile write time (when FU has said what to write to)
748 there is *one* unusual case here which has to be dealt with:
749 when the Function Unit does *NOT* request a write to the regfile
750 (has its data.ok bit CLEARED). this is perfectly legitimate.
753 comb
, sync
= m
.d
.comb
, m
.d
.sync
754 name
= "%s_%s_%d" % (funame
, regname
, idx
)
756 # connect up the bitvector write hazard. unlike the
757 # regfile writeports, a ONE must be written to the corresponding
758 # bit of the hazard bitvector (to indicate the existence of
761 # the detection of what shall be written to is based
762 # on *issue*. it is delayed by 1 cycle so that instructions
763 # "addi 5,5,0x2" do not cause combinatorial loops due to
764 # fake-dependency on *themselves*. this will totally fail
765 # spectacularly when doing multi-issue
766 print ("write vector (for regread)", regfile
, wvset
)
767 wviaddr_en
= Signal(len(wvset
), name
="wv_issue_addr_en_"+name
)
768 issue_active
= Signal(name
="iactive_"+name
)
769 sync
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
770 with m
.If(issue_active
):
772 comb
+= wviaddr_en
.eq(write
)
774 comb
+= wviaddr_en
.eq(1<<write
)
776 # deal with write vector clear: this kicks in when the regfile
777 # is written to, and clears the corresponding bitvector entry
778 print ("write vector", regfile
, wvclr
)
779 wvaddr_en
= Signal(len(wvclr
), name
="wvaddr_en_"+name
)
781 comb
+= wvaddr_en
.eq(addr_en
)
784 comb
+= wvaddr_en
.eq(1<<addr_en
)
786 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
787 # this may NOT be the case when an exception occurs
788 if isinstance(fu
, LDSTFunctionUnit
):
789 return wvaddr_en
, wviaddr_en
791 # okaaay, this is preparation for the awkward case.
792 # * latch a copy of wrflag when issue goes high.
793 # * when the fu_wrok (data.ok) flag is NOT set,
794 # but the FU is done, the FU is NEVER going to write
795 # so the bitvector has to be cleared.
796 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
797 with m
.If(~fu
.busy_o
):
798 sync
+= latch_wrflag
.eq(0)
799 with m
.If(fu
.issue_i
& fu_active
):
800 sync
+= latch_wrflag
.eq(wrflag
)
801 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
803 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
805 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
807 return wvaddr_en
, wviaddr_en
809 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
810 wrpickers
, regfile
, regname
, fspec
):
811 comb
, sync
= m
.d
.comb
, m
.d
.sync
817 # select the required write port. these are pre-defined sizes
818 rfile
= regs
.rf
[regfile
.lower()]
819 wport
= rfile
.w_ports
[rpidx
]
821 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
822 print(regfile
, regs
.rf
.keys())
824 # select the write-protection hazard vector. note that this still
825 # requires to WRITE to the hazard bitvector! read-requests need
826 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
827 if self
.make_hazard_vecs
:
828 wv
= regs
.wv
[regfile
.lower()]
829 wvset
= wv
.s
# write-vec bit-level hazard ctrl
830 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
831 wvchk
= wv
.q
# write-after-write hazard check
834 if not isinstance(fspecs
, list):
841 for i
, fspec
in enumerate(fspecs
):
842 # get the regfile specs for this regfile port
843 (wf
, _write
, wid
, fuspecs
) = \
844 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
845 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspecs
))
846 ppoffs
.append(pplen
) # record offset for picker
847 pplen
+= len(fuspecs
)
849 name
= "%s_%s_%d" % (regfile
, regname
, i
)
850 wrflag
= Signal(name
="wr_flag_"+name
)
852 comb
+= wrflag
.eq(wf
)
855 wrflags
.append(wrflag
)
857 # create a priority picker to manage this port
858 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
859 m
.submodules
["wrpick_%s_%s" % (regfile
, rpidx
)] = wrpick
866 #wvens = [] - not needed: reading of writevec is permanently held hi
868 for i
, fspec
in enumerate(fspecs
):
869 # connect up the FU req/go signals and the reg-read to the FU
870 # these are arbitrated by Data.ok signals
871 (wf
, _write
, wid
, fuspecs
) = \
872 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
873 for pi
, fuspec
in enumerate(fspec
.specs
):
874 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
875 fu_requested
= fu_bitdict
[funame
]
877 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
878 # get (or set up) a write-latched copy of write register number
879 write
= Signal
.like(_write
, name
="write_"+name
)
880 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
881 if rname
not in fu
.wr_latches
:
882 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
883 fu
.wr_latches
[rname
] = write
884 # do not depend on fu.issue_i here, it creates a
885 # combinatorial loop on waw checking. using the FU
886 # "enable" bitdict entry for this FU is sufficient,
887 # because the PowerDecoder2 read/write nums are
888 # valid continuously when the instruction is valid
889 with m
.If(fu_requested
):
890 sync
+= wrl
.eq(_write
)
891 comb
+= write
.eq(_write
)
893 comb
+= write
.eq(wrl
)
895 write
= fu
.wr_latches
[rname
]
897 # write-request comes from dest.ok
898 dest
= fu
.get_out(idx
)
899 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
900 name
= "%s_%s_%d" % (funame
, regname
, idx
)
901 fu_wrok
= Signal(name
="fu_wrok_"+name
, reset_less
=True)
902 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
904 # connect request-write to picker input, and output to go-wr
905 fu_active
= fu_selected
[funame
]
906 pick
= fu
.wr
.rel_o
[idx
] & fu_active
907 comb
+= wrpick
.i
[pi
].eq(pick
)
908 # create a single-pulse go write from the picker output
909 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
910 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
911 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
913 # connect the regspec write "reg select" number to this port
914 # only if one FU actually requests (and is granted) the port
915 # will the write-enable be activated
916 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
917 addr_en
= Signal
.like(write
, name
=wname
)
919 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
920 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
924 addrs
.append(addr_en
)
927 # connect regfile port to input
928 print("reg connect widths",
929 regfile
, regname
, pi
, funame
,
930 dest
.shape(), wport
.i_data
.shape())
931 wsigs
.append(fu_dest_latch
)
933 # now connect up the bitvector write hazard
934 if not self
.make_hazard_vecs
:
936 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
937 funame
, regname
, idx
,
938 addr_en
, wp
, fu
, fu_active
,
939 wrflags
[i
], write
, fu_wrok
)
940 wvaddr_en
, wv_issue_en
= res
941 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
942 wvseten
.append(wv_issue_en
) # set data same as enable
944 # read the write-hazard bitvector (wv) for any bit that is
945 fu_requested
= fu_bitdict
[funame
]
946 wvchk_en
= Signal(len(wvchk
), name
="waw_chk_addr_en_"+name
)
947 issue_active
= Signal(name
="waw_iactive_"+name
)
948 whazard
= Signal(name
="whaz_"+name
)
950 # XXX EEK! STATE regfile (branch) does not have an
951 # write-active indicator in regspec_decode_write()
952 print ("XXX FIXME waw_iactive", issue_active
,
955 # check bits from the incoming instruction. note (back
956 # in connect_instruction) that the decoder is held for
957 # us to be able to do this, here... *without* issue being
958 # held HI. we MUST NOT gate this with fu.issue_i or
959 # with fu_bitdict "enable": it would create a loop
960 comb
+= issue_active
.eq(wf
)
961 with m
.If(issue_active
):
963 comb
+= wvchk_en
.eq(write
)
965 comb
+= wvchk_en
.eq(1<<write
)
966 # if FU is busy (which doesn't get set at the same time as
967 # issue) and no hazard was detected, clear wvchk_en (i.e.
968 # stop checking for hazards). there is a loop here, but it's
969 # via a DFF, so is ok. some linters may complain, but hey.
970 with m
.If(fu
.busy_o
& ~whazard
):
971 comb
+= wvchk_en
.eq(0)
973 # write-hazard is ANDed with (filtered by) what is actually
974 # being requested. the wvchk data is on a one-clock delay,
975 # and wvchk_en comes directly from the main decoder
976 comb
+= whazard
.eq((wvchk
& wvchk_en
).bool())
978 comb
+= fu
._waw
_hazard
.eq(1)
980 #wvens.append(wvchk_en)
982 # here is where we create the Write Broadcast Bus. simple, eh?
983 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
985 # for unary-addressed
986 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
988 # for binary-addressed
989 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
990 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
992 if not self
.make_hazard_vecs
:
995 # return these here rather than set wvclr/wvset directly,
996 # because there may be more than one write-port to a given
997 # regfile. example: XER has a write-port for SO, CA, and OV
998 # and the *last one added* of those would overwrite the other
999 # two. solution: have connect_wrports collate all the
1000 # or-tree-reduced bitvector set/clear requests and drop them
1001 # in as a single "thing". this can only be done because the
1002 # set/get is an unary bitvector.
1003 print ("make write-vecs", regfile
, regname
, wvset
, wvclr
)
1004 return (wvclren
, # clear (regfile write)
1005 wvseten
) # set (issue time)
1007 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
1008 """connect write ports
1010 orders the write regspecs into a dict-of-dicts, by regfile,
1011 by regport name, then connects all FUs that want that regport
1012 by way of a PriorityPicker.
1014 note that the write-port wen, write-port data, and go_wr_i all need to
1015 be on the exact same clock cycle. as there is a combinatorial loop bug
1016 at the moment, these all use sync.
1018 comb
, sync
= m
.d
.comb
, m
.d
.sync
1021 # dictionary of lists of regfile write ports
1022 byregfiles_wrspec
= self
.get_byregfiles(m
, False)
1024 # same for write ports.
1025 # BLECH! complex code-duplication! BLECH!
1027 wvclrers
= defaultdict(list)
1028 wvseters
= defaultdict(list)
1029 for regfile
, fuspecs
in byregfiles_wrspec
.items():
1030 wrpickers
[regfile
] = {}
1032 if self
.regreduce_en
:
1033 # argh, more port-merging
1034 if regfile
== 'INT':
1035 fuspecs
['o'] = [fuspecs
.pop('o')]
1036 fuspecs
['o'].append(fuspecs
.pop('o1'))
1037 if regfile
== 'FAST':
1038 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
1039 if 'fast2' in fuspecs
:
1040 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
1041 if 'fast3' in fuspecs
:
1042 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
1044 # collate these and record them by regfile because there
1045 # are sometimes more write-ports per regfile
1046 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
1047 wvclren
, wvseten
= self
.connect_wrport(m
,
1048 fu_bitdict
, fu_selected
,
1050 regfile
, regname
, fspec
)
1051 wvclrers
[regfile
.lower()] += wvclren
1052 wvseters
[regfile
.lower()] += wvseten
1054 if not self
.make_hazard_vecs
:
1057 # for write-vectors: reduce the clr-ers and set-ers down to
1058 # a single set of bits. otherwise if there are two write
1059 # ports (on some regfiles), the last one doing comb += on
1060 # the reg.wv[regfile] instance "wins" (and all others are ignored,
1061 # whoops). if there was only one write-port per wv regfile this would
1063 for regfile
in wvclrers
.keys():
1064 wv
= regs
.wv
[regfile
]
1065 wvset
= wv
.s
# write-vec bit-level hazard ctrl
1066 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
1067 wvclren
= wvclrers
[regfile
]
1068 wvseten
= wvseters
[regfile
]
1069 comb
+= wvclr
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
1070 comb
+= wvset
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
1072 def get_byregfiles(self
, m
, readmode
):
1074 mode
= "read" if readmode
else "write"
1077 e
= self
.ireg
.e
# decoded instruction to execute
1079 # dictionary of dictionaries of lists/tuples of regfile ports.
1080 # first key: regfile. second key: regfile port name
1081 byregfiles_spec
= defaultdict(dict)
1083 for (funame
, fu
) in fus
.items():
1084 # create in each FU a receptacle for the read/write register
1085 # hazard numbers (and okflags for read). to be latched in
1086 # connect_rd/write_ports
1088 fu
.rd_latches
= {} # read reg number latches
1089 fu
.rf_latches
= {} # read flag latches
1093 # construct regfile specs: read uses inspec, write outspec
1094 print("%s ports for %s" % (mode
, funame
))
1095 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
1096 (regfile
, regname
, wid
) = fu
.get_io_spec(readmode
, idx
)
1097 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
1099 # the PowerDecoder2 (main one, not the satellites) contains
1100 # the decoded regfile numbers. obtain these now
1101 decinfo
= regspec_decode(m
, readmode
, e
, regfile
, regname
)
1102 okflag
, regport
= decinfo
.okflag
, decinfo
.regport
1104 # construct the dictionary of regspec information by regfile
1105 if regname
not in byregfiles_spec
[regfile
]:
1106 byregfiles_spec
[regfile
][regname
] = \
1107 ByRegSpec(okflag
, regport
, wid
, [])
1109 # here we start to create "lanes" where each Function Unit
1110 # requiring access to a given [single-contended resource]
1111 # regfile port is appended to a list, so that PriorityPickers
1112 # can be created to give uncontested access to it
1113 fuspec
= FUSpec(funame
, fu
, idx
)
1114 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
1116 # ok just print that all out, for convenience
1117 for regfile
, fuspecs
in byregfiles_spec
.items():
1118 print("regfile %s ports:" % mode
, regfile
)
1119 for regname
, fspec
in fuspecs
.items():
1120 [okflag
, regport
, wid
, fuspecs
] = fspec
1121 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
1122 print(" %s" % regname
, wid
, okflag
, regport
)
1123 for (funame
, fu
, idx
) in fuspecs
:
1124 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
1125 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
1128 return byregfiles_spec
1131 yield from self
.fus
.ports()
1132 yield from self
.i
.e
.ports()
1133 yield from self
.l0
.ports()
1140 if __name__
== '__main__':
1141 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
1147 dut
= NonProductionCore(pspec
)
1148 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
1149 with
open("test_core.il", "w") as f
: