src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp, Function
  43 from soc.config.state import CoreState
  44
  45 from collections import defaultdict
  46 import operator
  47
  48 from nmutil.util import rising_edge
  49
  50
  51 # helper function for reducing a list of signals down to a parallel
  52 # ORed single signal.
  53 def ortreereduce(tree, attr="o_data"):
  54     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  55
  56
  57 def ortreereduce_sig(tree):
  58     return treereduce(tree, operator.or_, lambda x: x)
  59
  60
  61 # helper function to place full regs declarations first
  62 def sort_fuspecs(fuspecs):
  63     res = []
  64     for (regname, fspec) in fuspecs.items():
  65         if regname.startswith("full"):
  66             res.append((regname, fspec))
  67     for (regname, fspec) in fuspecs.items():
  68         if not regname.startswith("full"):
  69             res.append((regname, fspec))
  70     return res  # enumerate(res)
  71
  72
  73 class CoreInput:
  74     """CoreInput: this is the input specification for Signals coming into core.
  75
  76     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  77       (TODO: bigendian_i should really be read from the relevant MSR bit)
  78
  79     * the previously-decoded instruction goes into the Decode2Execute1Type
  80       data structure. no need for Core to re-decode that.  however note
  81       that *satellite* decoders *are* part of Core.
  82
  83     * the raw instruction. this is used by satellite decoders internal to
  84       Core, to provide Function-Unit-specific information.  really, they
  85       should be part of the actual ALU itself (in order to reduce wires),
  86       but hey.
  87
  88     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  89       Vector context, etc.
  90     """
  91     def __init__(self, pspec, svp64_en, regreduce_en):
  92         self.pspec = pspec
  93         self.svp64_en = svp64_en
  94         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  95                                 regreduce_en=regreduce_en)
  96
  97         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  98         self.sv_a_nz = Signal()
  99
 100         # state and raw instruction (and SVP64 ReMap fields)
 101         self.state = CoreState("core")
 102         self.raw_insn_i = Signal(32) # raw instruction
 103         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 104         if svp64_en:
 105             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
 106             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
 107             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
 108             self.sv_pred_sm = Signal() # TODO: SIMD width
 109             self.sv_pred_dm = Signal() # TODO: SIMD width
 110
 111     def eq(self, i):
 112         self.e.eq(i.e)
 113         self.sv_a_nz.eq(i.sv_a_nz)
 114         self.state.eq(i.state)
 115         self.raw_insn_i.eq(i.raw_insn_i)
 116         self.bigendian_i.eq(i.bigendian_i)
 117         if not self.svp64_en:
 118             return
 119         self.sv_rm.eq(i.sv_rm)
 120         self.is_svp64_mode.eq(i.is_svp64_mode)
 121         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 122         self.sv_pred_sm.eq(i.sv_pred_sm)
 123         self.sv_pred_dm.eq(i.sv_pred_dm)
 124
 125
 126 class CoreOutput:
 127     def __init__(self):
 128         # start/stop and terminated signalling
 129         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 130         self.exc_happened = Signal()             # exception happened
 131
 132     def eq(self, i):
 133         self.core_terminate_o.eq(i.core_terminate_o)
 134         self.exc_happened.eq(i.exc_happened)
 135
 136
 137 # derive from ControlBase rather than have a separate Stage instance,
 138 # this is simpler to do
 139 class NonProductionCore(ControlBase):
 140     def __init__(self, pspec):
 141         self.pspec = pspec
 142
 143         # test is SVP64 is to be enabled
 144         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 145
 146         # test to see if regfile ports should be reduced
 147         self.regreduce_en = (hasattr(pspec, "regreduce") and
 148                              (pspec.regreduce == True))
 149
 150         super().__init__(stage=self)
 151
 152         # single LD/ST funnel for memory access
 153         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 154         pi = l0.l0.dports[0]
 155
 156         # function units (only one each)
 157         # only include mmu if enabled in pspec
 158         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 159
 160         # link LoadStore1 into MMU
 161         mmu = self.fus.get_fu('mmu0')
 162         print ("core pspec", pspec.ldst_ifacetype)
 163         print ("core mmu", mmu)
 164         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 165         if mmu is not None:
 166             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 167
 168         # register files (yes plural)
 169         self.regs = RegFiles(pspec)
 170
 171         # set up input and output: unusual requirement to set data directly
 172         # (due to the way that the core is set up in a different domain,
 173         # see TestIssuer.setup_peripherals
 174         self.i, self.o = self.new_specs(None)
 175         self.i, self.o = self.p.i_data, self.n.o_data
 176
 177         # create per-FU instruction decoders (subsetted)
 178         self.decoders = {}
 179         self.des = {}
 180
 181         for funame, fu in self.fus.fus.items():
 182             f_name = fu.fnunit.name
 183             fnunit = fu.fnunit.value
 184             opkls = fu.opsubsetkls
 185             if f_name == 'TRAP':
 186                 # TRAP decoder is the *main* decoder
 187                 self.trapunit = funame
 188                 continue
 189             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 190                                                       final=True,
 191                                                       state=self.i.state,
 192                                             svp64_en=self.svp64_en,
 193                                             regreduce_en=self.regreduce_en)
 194             self.des[funame] = self.decoders[funame].do
 195
 196         if "mmu0" in self.decoders:
 197             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 198
 199     def setup(self, m, i):
 200         pass
 201
 202     def ispec(self):
 203         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 204
 205     def ospec(self):
 206         return CoreOutput()
 207
 208     def elaborate(self, platform):
 209         m = super().elaborate(platform)
 210
 211         # for testing purposes, to cut down on build time in coriolis2
 212         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 213             x = Signal() # dummy signal
 214             m.d.sync += x.eq(~x)
 215             return m
 216         comb = m.d.comb
 217
 218         m.submodules.fus = self.fus
 219         m.submodules.l0 = l0 = self.l0
 220         self.regs.elaborate_into(m, platform)
 221         regs = self.regs
 222         fus = self.fus.fus
 223
 224         # connect decoders
 225         self.connect_satellite_decoders(m)
 226
 227         # ssh, cheat: trap uses the main decoder because of the rewriting
 228         self.des[self.trapunit] = self.i.e.do
 229
 230         # connect up Function Units, then read/write ports
 231         fu_bitdict = self.connect_instruction(m)
 232         self.connect_rdports(m, fu_bitdict)
 233         self.connect_wrports(m, fu_bitdict)
 234
 235         # note if an exception happened.  in a pipelined or OoO design
 236         # this needs to be accompanied by "shadowing" (or stalling)
 237         el = []
 238         for exc in self.fus.excs.values():
 239             el.append(exc.happened)
 240         if len(el) > 0: # at least one exception
 241             comb += self.o.exc_happened.eq(Cat(*el).bool())
 242
 243         return m
 244
 245     def connect_satellite_decoders(self, m):
 246         comb = m.d.comb
 247         for k, v in self.decoders.items():
 248             # connect each satellite decoder and give it the instruction.
 249             # as subset decoders this massively reduces wire fanout given
 250             # the large number of ALUs
 251             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 252             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 253             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 254             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 255             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 256             if self.svp64_en:
 257                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 258                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 259                 if k != self.trapunit:
 260                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 261                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 262                     # only the LDST PowerDecodeSubset *actually* needs to
 263                     # know to use the alternative decoder.  this is all
 264                     # a terrible hack
 265                     if k.lower().startswith("ldst"):
 266                         comb += v.use_svp64_ldst_dec.eq(
 267                                         self.i.use_svp64_ldst_dec)
 268
 269     def connect_instruction(self, m):
 270         """connect_instruction
 271
 272         uses decoded (from PowerOp) function unit information from CSV files
 273         to ascertain which Function Unit should deal with the current
 274         instruction.
 275
 276         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 277         ignoring it and halting the processor.  OP_NOP is a bit annoying
 278         because the issuer expects busy flag still to be raised then lowered.
 279         (this requires a fake counter to be set).
 280         """
 281         comb, sync = m.d.comb, m.d.sync
 282         fus = self.fus.fus
 283
 284         # indicate if core is busy
 285         busy_o = Signal(name="corebusy_o", reset_less=True)
 286
 287         # enable-signals for each FU, get one bit for each FU (by name)
 288         fu_enable = Signal(len(fus), reset_less=True)
 289         fu_bitdict = {}
 290         for i, funame in enumerate(fus.keys()):
 291             fu_bitdict[funame] = fu_enable[i]
 292
 293         # identify function units and create a list by fnunit so that
 294         # PriorityPickers can be created for selecting one of them that
 295         # isn't busy at the time the incoming instruction needs passing on
 296         by_fnunit = defaultdict(list)
 297         for fname, member in Function.__members__.items():
 298             for funame, fu in fus.items():
 299                 fnunit = fu.fnunit.value
 300                 if member.value & fnunit: # this FU handles this type of op
 301                     by_fnunit[fname].append(fu) # add FU to list, by FU name
 302
 303         # ok now just print out the list of FUs by Function, because we can
 304         for fname, fu_list in by_fnunit.items():
 305             print ("FUs by type", fname, fu_list)
 306
 307         # enable the required Function Unit based on the opcode decode
 308         # note: this *only* works correctly for simple core when one and
 309         # *only* one FU is allocated per instruction.  what is actually
 310         # required is one PriorityPicker per group of matching fnunits,
 311         # and for only one actual FU to be "picked".  this basically means
 312         # when ReservationStations are enabled it will be possible to
 313         # monitor multiple outstanding processing properly.
 314         for funame, fu in fus.items():
 315             fnunit = fu.fnunit.value
 316             enable = Signal(name="en_%s" % funame, reset_less=True)
 317             comb += enable.eq((self.i.e.do.fn_unit & fnunit).bool())
 318             comb += fu_bitdict[funame].eq(enable)
 319
 320         # sigh - need a NOP counter
 321         counter = Signal(2)
 322         with m.If(counter != 0):
 323             sync += counter.eq(counter - 1)
 324             comb += busy_o.eq(1)
 325
 326         with m.If(self.p.i_valid): # run only when valid
 327             with m.Switch(self.i.e.do.insn_type):
 328                 # check for ATTN: halt if true
 329                 with m.Case(MicrOp.OP_ATTN):
 330                     m.d.sync += self.o.core_terminate_o.eq(1)
 331
 332                 # fake NOP - this isn't really used (Issuer detects NOP)
 333                 with m.Case(MicrOp.OP_NOP):
 334                     sync += counter.eq(2)
 335                     comb += busy_o.eq(1)
 336
 337                 with m.Default():
 338                     # connect up instructions.  only one enabled at a time
 339                     for funame, fu in fus.items():
 340                         do = self.des[funame]
 341                         enable = fu_bitdict[funame]
 342
 343                         # run this FunctionUnit if enabled
 344                         # route op, issue, busy, read flags and mask to FU
 345                         with m.If(enable):
 346                             # operand comes from the *local*  decoder
 347                             comb += fu.oper_i.eq_from(do)
 348                             comb += fu.issue_i.eq(1) # issue when input valid
 349                             comb += busy_o.eq(fu.busy_o)
 350                             # rdmask, which is for registers, needs to come
 351                             # from the *main* decoder
 352                             rdmask = get_rdflags(self.i.e, fu)
 353                             comb += fu.rdmaskn.eq(~rdmask)
 354
 355         # if instruction is busy, set busy output for core.
 356         busys = map(lambda fu: fu.busy_o, fus.values())
 357         comb += busy_o.eq(Cat(*busys).bool())
 358
 359         # set ready/valid signalling.  if busy, means refuse incoming issue
 360         # XXX note: for an in-order core this is far too simple.  busy must
 361         # be gated with the *availability* of the incoming (requested)
 362         # instruction, where Core must be prepared to store-and-hold
 363         # an instruction if no FU is available.
 364         comb += self.p.o_ready.eq(~busy_o)
 365
 366         return fu_bitdict
 367
 368     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 369         comb, sync = m.d.comb, m.d.sync
 370         fus = self.fus.fus
 371         regs = self.regs
 372
 373         rpidx = regname
 374
 375         # select the required read port.  these are pre-defined sizes
 376         rfile = regs.rf[regfile.lower()]
 377         rport = rfile.r_ports[rpidx]
 378         print("read regfile", rpidx, regfile, regs.rf.keys(),
 379                               rfile, rfile.unary)
 380
 381         fspecs = fspec
 382         if not isinstance(fspecs, list):
 383             fspecs = [fspecs]
 384
 385         rdflags = []
 386         pplen = 0
 387         reads = []
 388         ppoffs = []
 389         for i, fspec in enumerate(fspecs):
 390             # get the regfile specs for this regfile port
 391             (rf, read, write, wid, fuspec) = fspec
 392             print ("fpsec", i, fspec, len(fuspec))
 393             ppoffs.append(pplen) # record offset for picker
 394             pplen += len(fuspec)
 395             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 396             rdflag = Signal(name=name, reset_less=True)
 397             comb += rdflag.eq(rf)
 398             rdflags.append(rdflag)
 399             reads.append(read)
 400
 401         print ("pplen", pplen)
 402
 403         # create a priority picker to manage this port
 404         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 405         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 406
 407         rens = []
 408         addrs = []
 409         for i, fspec in enumerate(fspecs):
 410             (rf, read, write, wid, fuspec) = fspec
 411             # connect up the FU req/go signals, and the reg-read to the FU
 412             # and create a Read Broadcast Bus
 413             for pi, (funame, fu, idx) in enumerate(fuspec):
 414                 pi += ppoffs[i]
 415
 416                 # connect request-read to picker input, and output to go-rd
 417                 fu_active = fu_bitdict[funame]
 418                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 419                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 420                 pick = Signal(name="pick_"+name)     # picker input
 421                 rp = Signal(name="rp_"+name)         # picker output
 422                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 423
 424                 # exclude any currently-enabled read-request (mask out active)
 425                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 426                                 ~delay_pick)
 427                 comb += rdpick.i[pi].eq(pick)
 428                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 429
 430                 # if picked, select read-port "reg select" number to port
 431                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 432                 sync += delay_pick.eq(rp) # delayed "pick"
 433                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 434
 435                 # the read-enable happens combinatorially (see mux-bus below)
 436                 # but it results in the data coming out on a one-cycle delay.
 437                 if rfile.unary:
 438                     rens.append(addr_en)
 439                 else:
 440                     addrs.append(addr_en)
 441                     rens.append(rp)
 442
 443                 # use the *delayed* pick signal to put requested data onto bus
 444                 with m.If(delay_pick):
 445                     # connect regfile port to input, creating fan-out Bus
 446                     src = fu.src_i[idx]
 447                     print("reg connect widths",
 448                           regfile, regname, pi, funame,
 449                           src.shape(), rport.o_data.shape())
 450                     # all FUs connect to same port
 451                     comb += src.eq(rport.o_data)
 452
 453         # or-reduce the muxed read signals
 454         if rfile.unary:
 455             # for unary-addressed
 456             comb += rport.ren.eq(ortreereduce_sig(rens))
 457         else:
 458             # for binary-addressed
 459             comb += rport.addr.eq(ortreereduce_sig(addrs))
 460             comb += rport.ren.eq(Cat(*rens).bool())
 461             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 462
 463     def connect_rdports(self, m, fu_bitdict):
 464         """connect read ports
 465
 466         orders the read regspecs into a dict-of-dicts, by regfile, by
 467         regport name, then connects all FUs that want that regport by
 468         way of a PriorityPicker.
 469         """
 470         comb, sync = m.d.comb, m.d.sync
 471         fus = self.fus.fus
 472         regs = self.regs
 473
 474         # dictionary of lists of regfile read ports
 475         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 476
 477         # okaay, now we need a PriorityPicker per regfile per regfile port
 478         # loootta pickers... peter piper picked a pack of pickled peppers...
 479         rdpickers = {}
 480         for regfile, spec in byregfiles_rd.items():
 481             fuspecs = byregfiles_rdspec[regfile]
 482             rdpickers[regfile] = {}
 483
 484             # argh.  an experiment to merge RA and RB in the INT regfile
 485             # (we have too many read/write ports)
 486             if self.regreduce_en:
 487                 if regfile == 'INT':
 488                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 489                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 490                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 491                 if regfile == 'FAST':
 492                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 493                     if 'fast2' in fuspecs:
 494                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 495                     if 'fast3' in fuspecs:
 496                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 497
 498             # for each named regfile port, connect up all FUs to that port
 499             for (regname, fspec) in sort_fuspecs(fuspecs):
 500                 print("connect rd", regname, fspec)
 501                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 502                                        regname, fspec)
 503
 504     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 505         comb, sync = m.d.comb, m.d.sync
 506         fus = self.fus.fus
 507         regs = self.regs
 508
 509         print("connect wr", regname, fspec)
 510         rpidx = regname
 511
 512         # select the required write port.  these are pre-defined sizes
 513         print(regfile, regs.rf.keys())
 514         rfile = regs.rf[regfile.lower()]
 515         wport = rfile.w_ports[rpidx]
 516
 517         fspecs = fspec
 518         if not isinstance(fspecs, list):
 519             fspecs = [fspecs]
 520
 521         pplen = 0
 522         writes = []
 523         ppoffs = []
 524         for i, fspec in enumerate(fspecs):
 525             # get the regfile specs for this regfile port
 526             (rf, read, write, wid, fuspec) = fspec
 527             print ("fpsec", i, fspec, len(fuspec))
 528             ppoffs.append(pplen) # record offset for picker
 529             pplen += len(fuspec)
 530
 531         # create a priority picker to manage this port
 532         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 533         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 534
 535         wsigs = []
 536         wens = []
 537         addrs = []
 538         for i, fspec in enumerate(fspecs):
 539             # connect up the FU req/go signals and the reg-read to the FU
 540             # these are arbitrated by Data.ok signals
 541             (rf, read, write, wid, fuspec) = fspec
 542             for pi, (funame, fu, idx) in enumerate(fuspec):
 543                 pi += ppoffs[i]
 544
 545                 # write-request comes from dest.ok
 546                 dest = fu.get_out(idx)
 547                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 548                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 549                 wrflag = Signal(name=name, reset_less=True)
 550                 comb += wrflag.eq(dest.ok & fu.busy_o)
 551
 552                 # connect request-write to picker input, and output to go-wr
 553                 fu_active = fu_bitdict[funame]
 554                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 555                 comb += wrpick.i[pi].eq(pick)
 556                 # create a single-pulse go write from the picker output
 557                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 558                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 559                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 560
 561                 # connect the regspec write "reg select" number to this port
 562                 # only if one FU actually requests (and is granted) the port
 563                 # will the write-enable be activated
 564                 addr_en = Signal.like(write)
 565                 wp = Signal()
 566                 comb += wp.eq(wr_pick & wrpick.en_o)
 567                 comb += addr_en.eq(Mux(wp, write, 0))
 568                 if rfile.unary:
 569                     wens.append(addr_en)
 570                 else:
 571                     addrs.append(addr_en)
 572                     wens.append(wp)
 573
 574                 # connect regfile port to input
 575                 print("reg connect widths",
 576                       regfile, regname, pi, funame,
 577                       dest.shape(), wport.i_data.shape())
 578                 wsigs.append(fu_dest_latch)
 579
 580         # here is where we create the Write Broadcast Bus. simple, eh?
 581         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 582         if rfile.unary:
 583             # for unary-addressed
 584             comb += wport.wen.eq(ortreereduce_sig(wens))
 585         else:
 586             # for binary-addressed
 587             comb += wport.addr.eq(ortreereduce_sig(addrs))
 588             comb += wport.wen.eq(ortreereduce_sig(wens))
 589
 590     def connect_wrports(self, m, fu_bitdict):
 591         """connect write ports
 592
 593         orders the write regspecs into a dict-of-dicts, by regfile,
 594         by regport name, then connects all FUs that want that regport
 595         by way of a PriorityPicker.
 596
 597         note that the write-port wen, write-port data, and go_wr_i all need to
 598         be on the exact same clock cycle.  as there is a combinatorial loop bug
 599         at the moment, these all use sync.
 600         """
 601         comb, sync = m.d.comb, m.d.sync
 602         fus = self.fus.fus
 603         regs = self.regs
 604         # dictionary of lists of regfile write ports
 605         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 606
 607         # same for write ports.
 608         # BLECH!  complex code-duplication! BLECH!
 609         wrpickers = {}
 610         for regfile, spec in byregfiles_wr.items():
 611             fuspecs = byregfiles_wrspec[regfile]
 612             wrpickers[regfile] = {}
 613
 614             if self.regreduce_en:
 615                 # argh, more port-merging
 616                 if regfile == 'INT':
 617                     fuspecs['o'] = [fuspecs.pop('o')]
 618                     fuspecs['o'].append(fuspecs.pop('o1'))
 619                 if regfile == 'FAST':
 620                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 621                     if 'fast2' in fuspecs:
 622                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 623                     if 'fast3' in fuspecs:
 624                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 625
 626             for (regname, fspec) in sort_fuspecs(fuspecs):
 627                 self.connect_wrport(m, fu_bitdict, wrpickers,
 628                                         regfile, regname, fspec)
 629
 630     def get_byregfiles(self, readmode):
 631
 632         mode = "read" if readmode else "write"
 633         regs = self.regs
 634         fus = self.fus.fus
 635         e = self.i.e # decoded instruction to execute
 636
 637         # dictionary of lists of regfile ports
 638         byregfiles = {}
 639         byregfiles_spec = {}
 640         for (funame, fu) in fus.items():
 641             print("%s ports for %s" % (mode, funame))
 642             for idx in range(fu.n_src if readmode else fu.n_dst):
 643                 if readmode:
 644                     (regfile, regname, wid) = fu.get_in_spec(idx)
 645                 else:
 646                     (regfile, regname, wid) = fu.get_out_spec(idx)
 647                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 648                 if readmode:
 649                     rdflag, read = regspec_decode_read(e, regfile, regname)
 650                     write = None
 651                 else:
 652                     rdflag, read = None, None
 653                     wrport, write = regspec_decode_write(e, regfile, regname)
 654                 if regfile not in byregfiles:
 655                     byregfiles[regfile] = {}
 656                     byregfiles_spec[regfile] = {}
 657                 if regname not in byregfiles_spec[regfile]:
 658                     byregfiles_spec[regfile][regname] = \
 659                         (rdflag, read, write, wid, [])
 660                 # here we start to create "lanes"
 661                 if idx not in byregfiles[regfile]:
 662                     byregfiles[regfile][idx] = []
 663                 fuspec = (funame, fu, idx)
 664                 byregfiles[regfile][idx].append(fuspec)
 665                 byregfiles_spec[regfile][regname][4].append(fuspec)
 666
 667         # ok just print that out, for convenience
 668         for regfile, spec in byregfiles.items():
 669             print("regfile %s ports:" % mode, regfile)
 670             fuspecs = byregfiles_spec[regfile]
 671             for regname, fspec in fuspecs.items():
 672                 [rdflag, read, write, wid, fuspec] = fspec
 673                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 674                 print("  %s" % regname, wid, read, write, rdflag)
 675                 for (funame, fu, idx) in fuspec:
 676                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 677                     print("    ", funame, fu, idx, fusig)
 678                     print()
 679
 680         return byregfiles, byregfiles_spec
 681
 682     def __iter__(self):
 683         yield from self.fus.ports()
 684         yield from self.i.e.ports()
 685         yield from self.l0.ports()
 686         # TODO: regs
 687
 688     def ports(self):
 689         return list(self)
 690
 691
 692 if __name__ == '__main__':
 693     pspec = TestMemPspec(ldst_ifacetype='testpi',
 694                          imem_ifacetype='',
 695                          addr_wid=48,
 696                          mask_wid=8,
 697                          reg_wid=64)
 698     dut = NonProductionCore(pspec)
 699     vl = rtlil.convert(dut, ports=dut.ports())
 700     with open("test_core.il", "w") as f:
 701         f.write(vl)