0efbc95b6470e02c6d31077301452b011ae6afdc
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
36 from soc
.debug
.jtag
import JTAG
37 from soc
.config
.pinouts
import get_pinspecs
38 from soc
.config
.state
import CoreState
39 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
40 from soc
.bus
.simple_gpio
import SimpleGPIO
41 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
42 from soc
.clock
.select
import ClockSelect
43 from soc
.clock
.dummypll
import DummyPLL
44 from soc
.sv
.svstate
import SVSTATERec
47 from nmutil
.util
import rising_edge
49 def get_insn(f_instr_o
, pc
):
50 if f_instr_o
.width
== 32:
53 # 64-bit: bit 2 of pc decides which word to select
54 return f_instr_o
.word_select(pc
[2], 32)
56 # gets state input or reads from state regfile
57 def state_get(m
, state_i
, name
, regfile
, regnum
):
61 res
= Signal(64, reset_less
=True, name
=name
)
62 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
63 sync
+= res_ok_delay
.eq(~state_i
.ok
)
64 with m
.If(state_i
.ok
):
65 # incoming override (start from pc_i)
66 comb
+= res
.eq(state_i
.data
)
68 # otherwise read StateRegs regfile for PC...
69 comb
+= regfile
.ren
.eq(1<<regnum
)
70 # ... but on a 1-clock delay
71 with m
.If(res_ok_delay
):
72 comb
+= res
.eq(regfile
.data_o
)
75 def get_predint(m
, mask
, name
):
76 """decode SVP64 predicate integer mask field to reg number and invert
77 this is identical to the equivalent function in ISACaller except that
78 it doesn't read the INT directly, it just decodes "what needs to be done"
79 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
81 * all1s is set to indicate that no mask is to be applied.
82 * regread indicates the GPR register number to be read
83 * invert is set to indicate that the register value is to be inverted
84 * unary indicates that the contents of the register is to be shifted 1<<r3
87 regread
= Signal(5, name
=name
+"regread")
88 invert
= Signal(name
=name
+"invert")
89 unary
= Signal(name
=name
+"unary")
90 all1s
= Signal(name
=name
+"all1s")
92 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
93 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
94 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
96 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
97 with m
.Case(SVP64PredInt
.R3
.value
):
99 with m
.Case(SVP64PredInt
.R3_N
.value
):
100 comb
+= regread
.eq(3)
102 with m
.Case(SVP64PredInt
.R10
.value
):
103 comb
+= regread
.eq(10)
104 with m
.Case(SVP64PredInt
.R10_N
.value
):
105 comb
+= regread
.eq(10)
107 with m
.Case(SVP64PredInt
.R30
.value
):
108 comb
+= regread
.eq(30)
109 with m
.Case(SVP64PredInt
.R30_N
.value
):
110 comb
+= regread
.eq(30)
112 return regread
, invert
, unary
, all1s
114 def get_predcr(m
, mask
, name
):
115 """decode SVP64 predicate CR to reg number field and invert status
116 this is identical to _get_predcr in ISACaller
119 idx
= Signal(2, name
=name
+"idx")
120 invert
= Signal(name
=name
+"crinvert")
122 with m
.Case(SVP64PredCR
.LT
.value
):
125 with m
.Case(SVP64PredCR
.GE
.value
):
128 with m
.Case(SVP64PredCR
.GT
.value
):
131 with m
.Case(SVP64PredCR
.LE
.value
):
134 with m
.Case(SVP64PredCR
.EQ
.value
):
137 with m
.Case(SVP64PredCR
.NE
.value
):
140 with m
.Case(SVP64PredCR
.SO
.value
):
143 with m
.Case(SVP64PredCR
.NS
.value
):
149 class TestIssuerInternal(Elaboratable
):
150 """TestIssuer - reads instructions from TestMemory and issues them
152 efficiency and speed is not the main goal here: functional correctness
153 and code clarity is. optimisations (which almost 100% interfere with
154 easy understanding) come later.
156 def __init__(self
, pspec
):
158 # test is SVP64 is to be enabled
159 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
161 # JTAG interface. add this right at the start because if it's
162 # added it *modifies* the pspec, by adding enable/disable signals
163 # for parts of the rest of the core
164 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
166 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
168 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
169 # add signals to pspec to enable/disable icache and dcache
170 # (or data and intstruction wishbone if icache/dcache not included)
171 # https://bugs.libre-soc.org/show_bug.cgi?id=520
172 # TODO: do we actually care if these are not domain-synchronised?
173 # honestly probably not.
174 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
175 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
176 self
.wb_sram_en
= self
.jtag
.wb_sram_en
178 self
.wb_sram_en
= Const(1)
180 # add 4k sram blocks?
181 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
182 pspec
.sram4x4kblock
== True)
186 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
189 # add interrupt controller?
190 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
192 self
.xics_icp
= XICS_ICP()
193 self
.xics_ics
= XICS_ICS()
194 self
.int_level_i
= self
.xics_ics
.int_level_i
196 # add GPIO peripheral?
197 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
199 self
.simple_gpio
= SimpleGPIO()
200 self
.gpio_o
= self
.simple_gpio
.gpio_o
202 # main instruction core. suitable for prototyping / demo only
203 self
.core
= core
= NonProductionCore(pspec
)
205 # instruction decoder. goes into Trap Record
206 pdecode
= create_pdecode()
207 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
208 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
209 opkls
=IssuerDecode2ToOperand
,
210 svp64_en
=self
.svp64_en
)
212 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
214 # Test Instruction memory
215 self
.imem
= ConfigFetchUnit(pspec
).fu
218 self
.dbg
= CoreDebug()
220 # instruction go/monitor
221 self
.pc_o
= Signal(64, reset_less
=True)
222 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
223 self
.svstate_i
= Data(32, "svstate_i") # ditto
224 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
225 self
.busy_o
= Signal(reset_less
=True)
226 self
.memerr_o
= Signal(reset_less
=True)
228 # STATE regfile read /write ports for PC, MSR, SVSTATE
229 staterf
= self
.core
.regs
.rf
['state']
230 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
231 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
232 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
233 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
234 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
236 # DMI interface access
237 intrf
= self
.core
.regs
.rf
['int']
238 crrf
= self
.core
.regs
.rf
['cr']
239 xerrf
= self
.core
.regs
.rf
['xer']
240 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
241 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
242 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
245 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
246 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
248 # hack method of keeping an eye on whether branch/trap set the PC
249 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
250 self
.state_nia
.wen
.name
= 'state_nia_wen'
252 # pulse to synchronize the simulator at instruction end
253 self
.insn_done
= Signal()
256 # store copies of predicate masks
257 self
.srcmask
= Signal(64)
258 self
.dstmask
= Signal(64)
260 def fetch_fsm(self
, m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
261 fetch_pc_ready_o
, fetch_pc_valid_i
,
262 fetch_insn_valid_o
, fetch_insn_ready_i
):
265 this FSM performs fetch of raw instruction data, partial-decodes
266 it 32-bit at a time to detect SVP64 prefixes, and will optionally
267 read a 2nd 32-bit quantity if that occurs.
271 pdecode2
= self
.pdecode2
272 cur_state
= self
.cur_state
273 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
275 msr_read
= Signal(reset
=1)
277 with m
.FSM(name
='fetch_fsm'):
280 with m
.State("IDLE"):
281 comb
+= fetch_pc_ready_o
.eq(1)
282 with m
.If(fetch_pc_valid_i
):
283 # instruction allowed to go: start by reading the PC
284 # capture the PC and also drop it into Insn Memory
285 # we have joined a pair of combinatorial memory
286 # lookups together. this is Generally Bad.
287 comb
+= self
.imem
.a_pc_i
.eq(pc
)
288 comb
+= self
.imem
.a_valid_i
.eq(1)
289 comb
+= self
.imem
.f_valid_i
.eq(1)
290 sync
+= cur_state
.pc
.eq(pc
)
291 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
293 # initiate read of MSR. arrives one clock later
294 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
295 sync
+= msr_read
.eq(0)
297 m
.next
= "INSN_READ" # move to "wait for bus" phase
299 # dummy pause to find out why simulation is not keeping up
300 with m
.State("INSN_READ"):
301 # one cycle later, msr/sv read arrives. valid only once.
302 with m
.If(~msr_read
):
303 sync
+= msr_read
.eq(1) # yeah don't read it again
304 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
305 with m
.If(self
.imem
.f_busy_o
): # zzz...
306 # busy: stay in wait-read
307 comb
+= self
.imem
.a_valid_i
.eq(1)
308 comb
+= self
.imem
.f_valid_i
.eq(1)
310 # not busy: instruction fetched
311 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
314 # decode the SVP64 prefix, if any
315 comb
+= svp64
.raw_opcode_in
.eq(insn
)
316 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
317 # pass the decoded prefix (if any) to PowerDecoder2
318 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
319 # remember whether this is a prefixed instruction, so
320 # the FSM can readily loop when VL==0
321 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
322 # calculate the address of the following instruction
323 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
324 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
325 with m
.If(~svp64
.is_svp64_mode
):
326 # with no prefix, store the instruction
327 # and hand it directly to the next FSM
328 sync
+= dec_opcode_i
.eq(insn
)
329 m
.next
= "INSN_READY"
331 # fetch the rest of the instruction from memory
332 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
333 comb
+= self
.imem
.a_valid_i
.eq(1)
334 comb
+= self
.imem
.f_valid_i
.eq(1)
335 m
.next
= "INSN_READ2"
337 # not SVP64 - 32-bit only
338 sync
+= nia
.eq(cur_state
.pc
+ 4)
339 sync
+= dec_opcode_i
.eq(insn
)
340 m
.next
= "INSN_READY"
342 with m
.State("INSN_READ2"):
343 with m
.If(self
.imem
.f_busy_o
): # zzz...
344 # busy: stay in wait-read
345 comb
+= self
.imem
.a_valid_i
.eq(1)
346 comb
+= self
.imem
.f_valid_i
.eq(1)
348 # not busy: instruction fetched
349 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
350 sync
+= dec_opcode_i
.eq(insn
)
351 m
.next
= "INSN_READY"
352 # TODO: probably can start looking at pdecode2.rm_dec
353 # here or maybe even in INSN_READ state, if svp64_mode
354 # detected, in order to trigger - and wait for - the
356 pmode
= pdecode2
.rm_dec
.predmode
358 if pmode != SVP64PredMode.ALWAYS.value:
359 fire predicate loading FSM and wait before
362 sync += self.srcmask.eq(-1) # set to all 1s
363 sync += self.dstmask.eq(-1) # set to all 1s
364 m.next = "INSN_READY"
367 with m
.State("INSN_READY"):
368 # hand over the instruction, to be decoded
369 comb
+= fetch_insn_valid_o
.eq(1)
370 with m
.If(fetch_insn_ready_i
):
373 def fetch_predicate_fsm(self
, m
,
374 pred_insn_valid_i
, pred_insn_ready_o
,
375 pred_mask_valid_o
, pred_mask_ready_i
):
376 """fetch_predicate_fsm - obtains (constructs in the case of CR)
377 src/dest predicate masks
379 https://bugs.libre-soc.org/show_bug.cgi?id=617
380 the predicates can be read here, by using IntRegs r_ports['pred']
381 or CRRegs r_ports['pred']. in the case of CRs it will have to
382 be done through multiple reads, extracting one relevant at a time.
383 later, a faster way would be to use the 32-bit-wide CR port but
384 this is more complex decoding, here. equivalent code used in
385 ISACaller is "from soc.decoder.isa.caller import get_predcr"
389 pdecode2
= self
.pdecode2
390 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
391 predmode
= rm_dec
.predmode
392 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
393 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
395 # elif predmode == CR:
396 # CR-src sidx, sinvert = get_predcr(m, srcpred)
397 # CR-dst didx, dinvert = get_predcr(m, dstpred)
398 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
399 # has to cope with first one then the other
400 # for cr_idx = FSM-state-loop(0..VL-1):
401 # FSM-state-trigger-CR-read:
402 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
403 # comb += cr_pred.ren.eq(cr_ren)
404 # FSM-state-1-clock-later-actual-Read:
405 # cr_field = Signal(4)
407 # # read the CR field, select the appropriate bit
408 # comb += cr_field.eq(cr_pred.data_o)
409 # comb += cr_bit.eq(cr_field.bit_select(idx)))
410 # # just like in branch BO tests
411 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
414 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
415 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
416 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
417 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
419 with m
.FSM(name
="fetch_predicate"):
421 with m
.State("FETCH_PRED_IDLE"):
422 comb
+= pred_insn_ready_o
.eq(1)
423 with m
.If(pred_insn_valid_i
):
424 with m
.If(predmode
== SVP64PredMode
.INT
):
425 # skip fetching destination mask register, when zero
427 sync
+= self
.dstmask
.eq(-1)
428 # directly go to fetch source mask register
429 # guaranteed not to be zero (otherwise predmode
430 # would be SVP64PredMode.ALWAYS, not INT)
431 comb
+= int_pred
.addr
.eq(sregread
)
432 comb
+= int_pred
.ren
.eq(1)
433 m
.next
= "INT_SRC_READ"
434 # fetch destination predicate register
436 comb
+= int_pred
.addr
.eq(dregread
)
437 comb
+= int_pred
.ren
.eq(1)
438 m
.next
= "INT_DST_READ"
440 sync
+= self
.srcmask
.eq(-1)
441 sync
+= self
.dstmask
.eq(-1)
442 m
.next
= "FETCH_PRED_DONE"
444 with m
.State("INT_DST_READ"):
445 # store destination mask
446 inv
= Repl(dinvert
, 64)
447 sync
+= self
.dstmask
.eq(self
.int_pred
.data_o ^ inv
)
448 # skip fetching source mask register, when zero
450 sync
+= self
.srcmask
.eq(-1)
451 m
.next
= "FETCH_PRED_DONE"
452 # fetch source predicate register
454 comb
+= int_pred
.addr
.eq(sregread
)
455 comb
+= int_pred
.ren
.eq(1)
456 m
.next
= "INT_SRC_READ"
458 with m
.State("INT_SRC_READ"):
460 inv
= Repl(sinvert
, 64)
461 sync
+= self
.srcmask
.eq(self
.int_pred
.data_o ^ inv
)
462 m
.next
= "FETCH_PRED_DONE"
464 with m
.State("FETCH_PRED_DONE"):
465 comb
+= pred_mask_valid_o
.eq(1)
466 with m
.If(pred_mask_ready_i
):
467 m
.next
= "FETCH_PRED_IDLE"
469 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
470 dbg
, core_rst
, is_svp64_mode
,
471 fetch_pc_ready_o
, fetch_pc_valid_i
,
472 fetch_insn_valid_o
, fetch_insn_ready_i
,
473 pred_insn_valid_i
, pred_insn_ready_o
,
474 pred_mask_valid_o
, pred_mask_ready_i
,
475 exec_insn_valid_i
, exec_insn_ready_o
,
476 exec_pc_valid_o
, exec_pc_ready_i
):
479 decode / issue FSM. this interacts with the "fetch" FSM
480 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
481 (outgoing). also interacts with the "execute" FSM
482 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
484 SVP64 RM prefixes have already been set up by the
485 "fetch" phase, so execute is fairly straightforward.
490 pdecode2
= self
.pdecode2
491 cur_state
= self
.cur_state
494 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
496 # for updating svstate (things like srcstep etc.)
497 update_svstate
= Signal() # set this (below) if updating
498 new_svstate
= SVSTATERec("new_svstate")
499 comb
+= new_svstate
.eq(cur_state
.svstate
)
501 # precalculate srcstep+1 and dststep+1
502 cur_srcstep
= cur_state
.svstate
.srcstep
503 cur_dststep
= cur_state
.svstate
.dststep
504 next_srcstep
= Signal
.like(cur_srcstep
)
505 next_dststep
= Signal
.like(cur_dststep
)
506 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
507 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
509 with m
.FSM(name
="issue_fsm"):
511 # sync with the "fetch" phase which is reading the instruction
512 # at this point, there is no instruction running, that
513 # could inadvertently update the PC.
514 with m
.State("ISSUE_START"):
515 # wait on "core stop" release, before next fetch
516 # need to do this here, in case we are in a VL==0 loop
517 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
518 comb
+= fetch_pc_valid_i
.eq(1) # tell fetch to start
519 with m
.If(fetch_pc_ready_o
): # fetch acknowledged us
522 # tell core it's stopped, and acknowledge debug handshake
523 comb
+= core
.core_stopped_i
.eq(1)
524 comb
+= dbg
.core_stopped_i
.eq(1)
525 # while stopped, allow updating the PC and SVSTATE
526 with m
.If(self
.pc_i
.ok
):
527 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
528 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
529 sync
+= pc_changed
.eq(1)
530 with m
.If(self
.svstate_i
.ok
):
531 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
532 comb
+= update_svstate
.eq(1)
533 sync
+= sv_changed
.eq(1)
535 # decode the instruction when it arrives
536 with m
.State("INSN_WAIT"):
537 comb
+= fetch_insn_ready_i
.eq(1)
538 with m
.If(fetch_insn_valid_o
):
539 # decode the instruction
540 sync
+= core
.e
.eq(pdecode2
.e
)
541 sync
+= core
.state
.eq(cur_state
)
542 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
543 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
544 # set RA_OR_ZERO detection in satellite decoders
545 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
546 # loop into ISSUE_START if it's a SVP64 instruction
547 # and VL == 0. this because VL==0 is a for-loop
548 # from 0 to 0 i.e. always, always a NOP.
549 cur_vl
= cur_state
.svstate
.vl
550 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
551 # update the PC before fetching the next instruction
552 # since we are in a VL==0 loop, no instruction was
553 # executed that we could be overwriting
554 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
555 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
556 comb
+= self
.insn_done
.eq(1)
557 m
.next
= "ISSUE_START"
559 m
.next
= "PRED_START" # start fetching the predicate
561 with m
.State("PRED_START"):
562 comb
+= pred_insn_valid_i
.eq(1) # tell fetch_pred to start
563 with m
.If(pred_insn_ready_o
): # fetch_pred acknowledged us
566 with m
.State("MASK_WAIT"):
567 comb
+= pred_mask_ready_i
.eq(1) # ready to receive the masks
568 with m
.If(pred_mask_valid_o
): # predication masks are ready
569 m
.next
= "INSN_EXECUTE"
571 # handshake with execution FSM, move to "wait" once acknowledged
572 with m
.State("INSN_EXECUTE"):
573 # with m.If(is_svp64_mode):
574 # TODO advance src/dst step to "skip" over predicated-out
575 # from self.srcmask and self.dstmask
576 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
577 # but still without exceeding VL in either case
578 # IMPORTANT: when changing src/dest step, have to
579 # jump to m.next = "DECODE_SV" to deal with the change in
582 with m
.If(is_svp64_mode
):
584 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
585 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
588 if not pred_src_zero:
589 if (((1<<cur_srcstep) & self.srcmask) == 0) and
591 comb += update_svstate.eq(1)
592 comb += new_svstate.srcstep.eq(next_srcstep)
593 sync += sv_changed.eq(1)
595 if not pred_dst_zero:
596 if (((1<<cur_dststep) & self.dstmask) == 0) and
598 comb += new_svstate.dststep.eq(next_dststep)
599 comb += update_svstate.eq(1)
600 sync += sv_changed.eq(1)
606 comb
+= exec_insn_valid_i
.eq(1) # trigger execute
607 with m
.If(exec_insn_ready_o
): # execute acknowledged us
608 m
.next
= "EXECUTE_WAIT"
610 with m
.State("EXECUTE_WAIT"):
611 # wait on "core stop" release, at instruction end
612 # need to do this here, in case we are in a VL>1 loop
613 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
614 comb
+= exec_pc_ready_i
.eq(1)
615 with m
.If(exec_pc_valid_o
):
617 # was this the last loop iteration?
619 cur_vl
= cur_state
.svstate
.vl
620 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
622 # if either PC or SVSTATE were changed by the previous
623 # instruction, go directly back to Fetch, without
624 # updating either PC or SVSTATE
625 with m
.If(pc_changed | sv_changed
):
626 m
.next
= "ISSUE_START"
628 # also return to Fetch, when no output was a vector
629 # (regardless of SRCSTEP and VL), or when the last
630 # instruction was really the last one of the VL loop
631 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
632 # before going back to fetch, update the PC state
633 # register with the NIA.
634 # ok here we are not reading the branch unit.
635 # TODO: this just blithely overwrites whatever
636 # pipeline updated the PC
637 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
638 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
639 # reset SRCSTEP before returning to Fetch
640 with m
.If(pdecode2
.loop_continue
):
641 comb
+= new_svstate
.srcstep
.eq(0)
642 comb
+= new_svstate
.dststep
.eq(0)
643 comb
+= update_svstate
.eq(1)
644 m
.next
= "ISSUE_START"
646 # returning to Execute? then, first update SRCSTEP
648 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
649 comb
+= new_svstate
.dststep
.eq(next_dststep
)
650 comb
+= update_svstate
.eq(1)
654 comb
+= core
.core_stopped_i
.eq(1)
655 comb
+= dbg
.core_stopped_i
.eq(1)
656 # while stopped, allow updating the PC and SVSTATE
657 with m
.If(self
.pc_i
.ok
):
658 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
659 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
660 sync
+= pc_changed
.eq(1)
661 with m
.If(self
.svstate_i
.ok
):
662 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
663 comb
+= update_svstate
.eq(1)
664 sync
+= sv_changed
.eq(1)
666 # need to decode the instruction again, after updating SRCSTEP
667 # in the previous state.
668 # mostly a copy of INSN_WAIT, but without the actual wait
669 with m
.State("DECODE_SV"):
670 # decode the instruction
671 sync
+= core
.e
.eq(pdecode2
.e
)
672 sync
+= core
.state
.eq(cur_state
)
673 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
674 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
675 m
.next
= "INSN_EXECUTE" # move to "execute"
677 # check if svstate needs updating: if so, write it to State Regfile
678 with m
.If(update_svstate
):
679 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
680 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
681 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
683 def execute_fsm(self
, m
, core
, pc_changed
, sv_changed
,
684 exec_insn_valid_i
, exec_insn_ready_o
,
685 exec_pc_valid_o
, exec_pc_ready_i
):
688 execute FSM. this interacts with the "issue" FSM
689 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
690 (outgoing). SVP64 RM prefixes have already been set up by the
691 "issue" phase, so execute is fairly straightforward.
696 pdecode2
= self
.pdecode2
699 core_busy_o
= core
.busy_o
# core is busy
700 core_ivalid_i
= core
.ivalid_i
# instruction is valid
701 core_issue_i
= core
.issue_i
# instruction is issued
702 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
704 with m
.FSM(name
="exec_fsm"):
706 # waiting for instruction bus (stays there until not busy)
707 with m
.State("INSN_START"):
708 comb
+= exec_insn_ready_o
.eq(1)
709 with m
.If(exec_insn_valid_i
):
710 comb
+= core_ivalid_i
.eq(1) # instruction is valid
711 comb
+= core_issue_i
.eq(1) # and issued
712 sync
+= sv_changed
.eq(0)
713 sync
+= pc_changed
.eq(0)
714 m
.next
= "INSN_ACTIVE" # move to "wait completion"
716 # instruction started: must wait till it finishes
717 with m
.State("INSN_ACTIVE"):
718 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
719 comb
+= core_ivalid_i
.eq(1) # instruction is valid
720 # note changes to PC and SVSTATE
721 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.SVSTATE
)):
722 sync
+= sv_changed
.eq(1)
723 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
724 sync
+= pc_changed
.eq(1)
725 with m
.If(~core_busy_o
): # instruction done!
726 comb
+= exec_pc_valid_o
.eq(1)
727 with m
.If(exec_pc_ready_i
):
728 comb
+= self
.insn_done
.eq(1)
729 m
.next
= "INSN_START" # back to fetch
731 def setup_peripherals(self
, m
):
732 comb
, sync
= m
.d
.comb
, m
.d
.sync
734 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
735 m
.submodules
.imem
= imem
= self
.imem
736 m
.submodules
.dbg
= dbg
= self
.dbg
738 m
.submodules
.jtag
= jtag
= self
.jtag
739 # TODO: UART2GDB mux, here, from external pin
740 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
741 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
743 cur_state
= self
.cur_state
745 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
747 for i
, sram
in enumerate(self
.sram4k
):
748 m
.submodules
["sram4k_%d" % i
] = sram
749 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
751 # XICS interrupt handler
753 m
.submodules
.xics_icp
= icp
= self
.xics_icp
754 m
.submodules
.xics_ics
= ics
= self
.xics_ics
755 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
756 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
758 # GPIO test peripheral
760 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
762 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
763 # XXX causes litex ECP5 test to get wrong idea about input and output
764 # (but works with verilator sim *sigh*)
765 #if self.gpio and self.xics:
766 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
768 # instruction decoder
769 pdecode
= create_pdecode()
770 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
772 m
.submodules
.svp64
= svp64
= self
.svp64
775 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
776 intrf
= self
.core
.regs
.rf
['int']
778 # clock delay power-on reset
779 cd_por
= ClockDomain(reset_less
=True)
780 cd_sync
= ClockDomain()
781 core_sync
= ClockDomain("coresync")
782 m
.domains
+= cd_por
, cd_sync
, core_sync
784 ti_rst
= Signal(reset_less
=True)
785 delay
= Signal(range(4), reset
=3)
786 with m
.If(delay
!= 0):
787 m
.d
.por
+= delay
.eq(delay
- 1)
788 comb
+= cd_por
.clk
.eq(ClockSignal())
790 # power-on reset delay
791 core_rst
= ResetSignal("coresync")
792 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
793 comb
+= core_rst
.eq(ti_rst
)
795 # busy/halted signals from core
796 comb
+= self
.busy_o
.eq(core
.busy_o
)
797 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
799 # temporary hack: says "go" immediately for both address gen and ST
801 ldst
= core
.fus
.fus
['ldst0']
802 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
803 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
804 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
808 def elaborate(self
, platform
):
811 comb
, sync
= m
.d
.comb
, m
.d
.sync
812 cur_state
= self
.cur_state
813 pdecode2
= self
.pdecode2
817 # set up peripherals and core
818 core_rst
= self
.setup_peripherals(m
)
820 # PC and instruction from I-Memory
821 comb
+= self
.pc_o
.eq(cur_state
.pc
)
822 pc_changed
= Signal() # note write to PC
823 sv_changed
= Signal() # note write to SVSTATE
825 # read state either from incoming override or from regfile
826 # TODO: really should be doing MSR in the same way
827 pc
= state_get(m
, self
.pc_i
, "pc", # read PC
828 self
.state_r_pc
, StateRegs
.PC
)
829 svstate
= state_get(m
, self
.svstate_i
, "svstate", # read SVSTATE
830 self
.state_r_sv
, StateRegs
.SVSTATE
)
832 # don't write pc every cycle
833 comb
+= self
.state_w_pc
.wen
.eq(0)
834 comb
+= self
.state_w_pc
.data_i
.eq(0)
836 # don't read msr every cycle
837 comb
+= self
.state_r_msr
.ren
.eq(0)
839 # address of the next instruction, in the absence of a branch
840 # depends on the instruction size
841 nia
= Signal(64, reset_less
=True)
843 # connect up debug signals
844 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
845 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
846 comb
+= dbg
.state
.pc
.eq(pc
)
847 comb
+= dbg
.state
.svstate
.eq(svstate
)
848 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
850 # pass the prefix mode from Fetch to Issue, so the latter can loop
852 is_svp64_mode
= Signal()
854 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
855 # these are the handshake signals between fetch and decode/execute
857 # fetch FSM can run as soon as the PC is valid
858 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
859 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
861 # fetch FSM hands over the instruction to be decoded / issued
862 fetch_insn_valid_o
= Signal()
863 fetch_insn_ready_i
= Signal()
865 # predicate fetch FSM decodes and fetches the predicate
866 pred_insn_valid_i
= Signal()
867 pred_insn_ready_o
= Signal()
869 # predicate fetch FSM delivers the masks
870 pred_mask_valid_o
= Signal()
871 pred_mask_ready_i
= Signal()
873 # issue FSM delivers the instruction to the be executed
874 exec_insn_valid_i
= Signal()
875 exec_insn_ready_o
= Signal()
877 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
878 exec_pc_valid_o
= Signal()
879 exec_pc_ready_i
= Signal()
881 # the FSMs here are perhaps unusual in that they detect conditions
882 # then "hold" information, combinatorially, for the core
883 # (as opposed to using sync - which would be on a clock's delay)
884 # this includes the actual opcode, valid flags and so on.
886 # Fetch, then predicate fetch, then Issue, then Execute.
887 # Issue is where the VL for-loop # lives. the ready/valid
888 # signalling is used to communicate between the four.
890 self
.fetch_fsm(m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
891 fetch_pc_ready_o
, fetch_pc_valid_i
,
892 fetch_insn_valid_o
, fetch_insn_ready_i
)
894 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
895 dbg
, core_rst
, is_svp64_mode
,
896 fetch_pc_ready_o
, fetch_pc_valid_i
,
897 fetch_insn_valid_o
, fetch_insn_ready_i
,
898 pred_insn_valid_i
, pred_insn_ready_o
,
899 pred_mask_valid_o
, pred_mask_ready_i
,
900 exec_insn_valid_i
, exec_insn_ready_o
,
901 exec_pc_valid_o
, exec_pc_ready_i
)
903 self
.fetch_predicate_fsm(m
,
904 pred_insn_valid_i
, pred_insn_ready_o
,
905 pred_mask_valid_o
, pred_mask_ready_i
)
907 self
.execute_fsm(m
, core
, pc_changed
, sv_changed
,
908 exec_insn_valid_i
, exec_insn_ready_o
,
909 exec_pc_valid_o
, exec_pc_ready_i
)
911 # this bit doesn't have to be in the FSM: connect up to read
912 # regfiles on demand from DMI
915 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
916 # (which uses that in PowerDecoder2 to raise 0x900 exception)
917 self
.tb_dec_fsm(m
, cur_state
.dec
)
921 def do_dmi(self
, m
, dbg
):
922 """deals with DMI debug requests
924 currently only provides read requests for the INT regfile, CR and XER
925 it will later also deal with *writing* to these regfiles.
929 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
930 intrf
= self
.core
.regs
.rf
['int']
932 with m
.If(d_reg
.req
): # request for regfile access being made
933 # TODO: error-check this
934 # XXX should this be combinatorial? sync better?
936 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
938 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
939 comb
+= self
.int_r
.ren
.eq(1)
940 d_reg_delay
= Signal()
941 sync
+= d_reg_delay
.eq(d_reg
.req
)
942 with m
.If(d_reg_delay
):
943 # data arrives one clock later
944 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
945 comb
+= d_reg
.ack
.eq(1)
947 # sigh same thing for CR debug
948 with m
.If(d_cr
.req
): # request for regfile access being made
949 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
950 d_cr_delay
= Signal()
951 sync
+= d_cr_delay
.eq(d_cr
.req
)
952 with m
.If(d_cr_delay
):
953 # data arrives one clock later
954 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
955 comb
+= d_cr
.ack
.eq(1)
958 with m
.If(d_xer
.req
): # request for regfile access being made
959 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
960 d_xer_delay
= Signal()
961 sync
+= d_xer_delay
.eq(d_xer
.req
)
962 with m
.If(d_xer_delay
):
963 # data arrives one clock later
964 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
965 comb
+= d_xer
.ack
.eq(1)
967 def tb_dec_fsm(self
, m
, spr_dec
):
970 this is a FSM for updating either dec or tb. it runs alternately
971 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
972 value to DEC, however the regfile has "passthrough" on it so this
975 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
978 comb
, sync
= m
.d
.comb
, m
.d
.sync
979 fast_rf
= self
.core
.regs
.rf
['fast']
980 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
981 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
985 # initiates read of current DEC
986 with m
.State("DEC_READ"):
987 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
988 comb
+= fast_r_dectb
.ren
.eq(1)
991 # waits for DEC read to arrive (1 cycle), updates with new value
992 with m
.State("DEC_WRITE"):
994 # TODO: MSR.LPCR 32-bit decrement mode
995 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
996 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
997 comb
+= fast_w_dectb
.wen
.eq(1)
998 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
999 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
1002 # initiates read of current TB
1003 with m
.State("TB_READ"):
1004 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
1005 comb
+= fast_r_dectb
.ren
.eq(1)
1008 # waits for read TB to arrive, initiates write of current TB
1009 with m
.State("TB_WRITE"):
1011 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
1012 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
1013 comb
+= fast_w_dectb
.wen
.eq(1)
1014 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
1020 yield from self
.pc_i
.ports()
1023 yield from self
.core
.ports()
1024 yield from self
.imem
.ports()
1025 yield self
.core_bigendian_i
1031 def external_ports(self
):
1032 ports
= self
.pc_i
.ports()
1033 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
1037 ports
+= list(self
.jtag
.external_ports())
1039 # don't add DMI if JTAG is enabled
1040 ports
+= list(self
.dbg
.dmi
.ports())
1042 ports
+= list(self
.imem
.ibus
.fields
.values())
1043 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
1046 for sram
in self
.sram4k
:
1047 ports
+= list(sram
.bus
.fields
.values())
1050 ports
+= list(self
.xics_icp
.bus
.fields
.values())
1051 ports
+= list(self
.xics_ics
.bus
.fields
.values())
1052 ports
.append(self
.int_level_i
)
1055 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
1056 ports
.append(self
.gpio_o
)
1064 class TestIssuer(Elaboratable
):
1065 def __init__(self
, pspec
):
1066 self
.ti
= TestIssuerInternal(pspec
)
1068 self
.pll
= DummyPLL()
1070 # PLL direct clock or not
1071 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1073 self
.pll_18_o
= Signal(reset_less
=True)
1075 def elaborate(self
, platform
):
1079 # TestIssuer runs at direct clock
1080 m
.submodules
.ti
= ti
= self
.ti
1081 cd_int
= ClockDomain("coresync")
1084 # ClockSelect runs at PLL output internal clock rate
1085 m
.submodules
.pll
= pll
= self
.pll
1087 # add clock domains from PLL
1088 cd_pll
= ClockDomain("pllclk")
1091 # PLL clock established. has the side-effect of running clklsel
1092 # at the PLL's speed (see DomainRenamer("pllclk") above)
1093 pllclk
= ClockSignal("pllclk")
1094 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1096 # wire up external 24mhz to PLL
1097 comb
+= pll
.clk_24_i
.eq(ClockSignal())
1099 # output 18 mhz PLL test signal
1100 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
1102 # now wire up ResetSignals. don't mind them being in this domain
1103 pll_rst
= ResetSignal("pllclk")
1104 comb
+= pll_rst
.eq(ResetSignal())
1106 # internal clock is set to selector clock-out. has the side-effect of
1107 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1108 intclk
= ClockSignal("coresync")
1110 comb
+= intclk
.eq(pll
.clk_pll_o
)
1112 comb
+= intclk
.eq(ClockSignal())
1117 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1118 [ClockSignal(), ResetSignal()]
1120 def external_ports(self
):
1121 ports
= self
.ti
.external_ports()
1122 ports
.append(ClockSignal())
1123 ports
.append(ResetSignal())
1125 ports
.append(self
.pll
.clk_sel_i
)
1126 ports
.append(self
.pll_18_o
)
1127 ports
.append(self
.pll
.pll_lck_o
)
1131 if __name__
== '__main__':
1132 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1138 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1139 imem_ifacetype
='bare_wb',
1144 dut
= TestIssuer(pspec
)
1145 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1147 if len(sys
.argv
) == 1:
1148 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1149 with
open("test_issuer.il", "w") as f
: