src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from openpower.consts import MSR
   8 from soc.config.test.test_loadstore import TestMemPspec
   9 from soc.simple.issuer import TestIssuer
  10
  11
  12 if __name__ == '__main__':
  13     parser = argparse.ArgumentParser(description="Simple core issuer " \
  14                                      "verilog generator")
  15     parser.add_argument("output_filename")
  16     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  17                         help="Enable interrupts",
  18                         default=True)
  19     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  20                         help="Disable interrupts",
  21                         default=False)
  22     parser.add_argument("--enable-lessports", dest='lessports',
  23                         action="store_true",
  24                         help="Enable less regfile ports",
  25                         default=True)
  26     parser.add_argument("--disable-lessports", dest='lessports',
  27                         action="store_false",
  28                         help="enable more regfile ports",
  29                         default=False)
  30     parser.add_argument("--enable-core", dest='core', action="store_true",
  31                         help="Enable main core",
  32                         default=True)
  33     parser.add_argument("--disable-core", dest='core', action="store_false",
  34                         help="disable main core",
  35                         default=False)
  36     parser.add_argument("--enable-mmu", dest='mmu', action="store_true",
  37                         help="Enable mmu",
  38                         default=False)
  39     parser.add_argument("--disable-mmu", dest='mmu', action="store_false",
  40                         help="Disable mmu",
  41                         default=False)
  42     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  43                         help="Enable pll",
  44                         default=False)
  45     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  46                         help="Disable pll",
  47                         default=False)
  48     parser.add_argument("--enable-testgpio", action="store_true",
  49                         help="Disable gpio pins",
  50                         default=False)
  51     parser.add_argument("--enable-sram4x4kblock", action="store_true",
  52                         help="Disable sram 4x4k block",
  53                         default=False)
  54     parser.add_argument("--debug", default="jtag", help="Select debug " \
  55                         "interface [jtag | dmi] [default jtag]")
  56     parser.add_argument("--enable-svp64", dest='svp64', action="store_true",
  57                         help="Enable SVP64",
  58                         default=True)
  59     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
  60                         help="disable SVP64",
  61                         default=False)
  62
  63     args = parser.parse_args()
  64
  65     print(args)
  66
  67     units = {'alu': 1,
  68              'cr': 1, 'branch': 1, 'trap': 1,
  69              'logical': 1,
  70              'spr': 1,
  71              'div': 1,
  72              'mul': 1,
  73              'shiftrot': 1
  74             }
  75     if args.mmu:
  76         units['mmu'] = 1 # enable MMU
  77
  78     # decide which memory type to configure
  79     if args.mmu:
  80         ldst_ifacetype = 'mmu_cache_wb'
  81         imem_ifacetype = 'mmu_cache_wb'
  82     else:
  83         ldst_ifacetype = 'bare_wb'
  84         imem_ifacetype = 'bare_wb'
  85
  86     # default MSR (TODO, provide option to set default PC as well)
  87     msr_reset = (1<<MSR.LE) | (1<<MSR.SF) # 64-bit, little-endian default
  88
  89     pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
  90                          imem_ifacetype=imem_ifacetype,
  91                          addr_wid=48,
  92                          mask_wid=8,
  93                          # must leave at 64
  94                          reg_wid=64,
  95                          # set to 32 for instruction-memory width=32
  96                          imem_reg_wid=64,
  97                          # set to 32 to make data wishbone bus 32-bit
  98                          #wb_data_wid=32,
  99                          xics=args.xics, # XICS interrupt controller
 100                          nocore=not args.core, # test coriolis2 ioring
 101                          regreduce = args.lessports, # less regfile ports
 102                          use_pll=args.pll,  # bypass PLL
 103                          gpio=args.enable_testgpio, # for test purposes
 104                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
 105                          debug=args.debug,      # set to jtag or dmi
 106                          svp64=args.svp64,      # enable SVP64
 107                          microwatt_mmu=args.mmu,          # enable MMU
 108                          units=units,
 109                          msr_reset=msr_reset)
 110
 111     print("mmu", pspec.__dict__["microwatt_mmu"])
 112     print("nocore", pspec.__dict__["nocore"])
 113     print("regreduce", pspec.__dict__["regreduce"])
 114     print("gpio", pspec.__dict__["gpio"])
 115     print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
 116     print("xics", pspec.__dict__["xics"])
 117     print("use_pll", pspec.__dict__["use_pll"])
 118     print("debug", pspec.__dict__["debug"])
 119     print("SVP64", pspec.__dict__["svp64"])
 120
 121     dut = TestIssuer(pspec)
 122
 123     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
 124     with open(args.output_filename, "w") as f:
 125         f.write(vl)