src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from openpower.consts import MSR
   8 from soc.config.test.test_loadstore import TestMemPspec
   9 from soc.simple.issuer import TestIssuer, TestIssuerInternal
  10
  11
  12 if __name__ == '__main__':
  13     parser = argparse.ArgumentParser(description="Simple core issuer " \
  14                                      "verilog generator")
  15     parser.add_argument("output_filename")
  16     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  17                         help="Enable interrupts",
  18                         default=True)
  19     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  20                         help="Disable interrupts",
  21                         default=False)
  22     parser.add_argument("--enable-lessports", dest='lessports',
  23                         action="store_true",
  24                         help="Enable less regfile ports",
  25                         default=True)
  26     parser.add_argument("--disable-lessports", dest='lessports',
  27                         action="store_false",
  28                         help="enable more regfile ports",
  29                         default=False)
  30     parser.add_argument("--enable-core", dest='core', action="store_true",
  31                         help="Enable main core",
  32                         default=True)
  33     parser.add_argument("--disable-core", dest='core', action="store_false",
  34                         help="disable main core",
  35                         default=False)
  36     parser.add_argument("--enable-mmu", dest='mmu', action="store_true",
  37                         help="Enable mmu",
  38                         default=False)
  39     parser.add_argument("--disable-mmu", dest='mmu', action="store_false",
  40                         help="Disable mmu",
  41                         default=False)
  42     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  43                         help="Enable pll",
  44                         default=False)
  45     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  46                         help="Disable pll",
  47                         default=False)
  48     parser.add_argument("--enable-testgpio", action="store_true",
  49                         help="Disable gpio pins",
  50                         default=False)
  51     parser.add_argument("--enable-sram4x4kblock", action="store_true",
  52                         help="Disable sram 4x4k block",
  53                         default=False)
  54     parser.add_argument("--debug", default="jtag", help="Select debug " \
  55                         "interface [jtag | dmi] [default jtag]")
  56     parser.add_argument("--enable-svp64", dest='svp64', action="store_true",
  57                         help="Enable SVP64",
  58                         default=True)
  59     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
  60                         help="disable SVP64",
  61                         default=False)
  62     # create a module that's directly compatible as a drop-in replacement
  63     # in microwatt.v
  64     parser.add_argument("--microwatt-compat", dest='mwcompat',
  65                         action="store_true",
  66                         help="generate microwatt-compatible interface",
  67                         default=False)
  68
  69     args = parser.parse_args()
  70
  71     # convenience: set some defaults
  72     if args.mwcompat:
  73         args.pll = False
  74         args.debug = 'dmi'
  75         args.core = True
  76         args.xics = False
  77         args.gpio = False
  78         args.sram4x4kblock = False
  79         args.svp64 = False
  80
  81     print(args)
  82
  83     units = {'alu': 1,
  84              'cr': 1, 'branch': 1, 'trap': 1,
  85              'logical': 1,
  86              'spr': 1,
  87              'div': 1,
  88              'mul': 1,
  89              'shiftrot': 1
  90             }
  91     if args.mmu:
  92         units['mmu'] = 1 # enable MMU
  93
  94     # decide which memory type to configure
  95     if args.mmu:
  96         ldst_ifacetype = 'mmu_cache_wb'
  97         imem_ifacetype = 'mmu_cache_wb'
  98     else:
  99         ldst_ifacetype = 'bare_wb'
 100         imem_ifacetype = 'bare_wb'
 101
 102     # default MSR (TODO, provide option to set default PC as well)
 103     msr_reset = (1<<MSR.LE) | (1<<MSR.SF) # 64-bit, little-endian default
 104
 105     pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 106                          imem_ifacetype=imem_ifacetype,
 107                          addr_wid=64,
 108                          mask_wid=8,
 109                          # must leave at 64
 110                          reg_wid=64,
 111                          # set to 32 for instruction-memory width=32
 112                          imem_reg_wid=64,
 113                          # set to 32 to make data wishbone bus 32-bit
 114                          #wb_data_wid=32,
 115                          xics=args.xics, # XICS interrupt controller
 116                          nocore=not args.core, # test coriolis2 ioring
 117                          regreduce = args.lessports, # less regfile ports
 118                          use_pll=args.pll,  # bypass PLL
 119                          gpio=args.enable_testgpio, # for test purposes
 120                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
 121                          debug=args.debug,      # set to jtag or dmi
 122                          svp64=args.svp64,      # enable SVP64
 123                          microwatt_mmu=args.mmu,         # enable MMU
 124                          microwatt_compat=args.mwcompat, # microwatt compatible
 125                          units=units,
 126                          msr_reset=msr_reset)
 127     #if args.mwcompat:
 128     #    pspec.core_domain = 'sync'
 129
 130     print("mmu", pspec.__dict__["microwatt_mmu"])
 131     print("nocore", pspec.__dict__["nocore"])
 132     print("regreduce", pspec.__dict__["regreduce"])
 133     print("gpio", pspec.__dict__["gpio"])
 134     print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
 135     print("xics", pspec.__dict__["xics"])
 136     print("use_pll", pspec.__dict__["use_pll"])
 137     print("debug", pspec.__dict__["debug"])
 138     print("SVP64", pspec.__dict__["svp64"])
 139     print("Microwatt compatibility", pspec.__dict__["microwatt_compat"])
 140
 141     if args.mwcompat:
 142         dut = TestIssuerInternal(pspec)
 143         name = "external_core_top"
 144     else:
 145         dut = TestIssuer(pspec)
 146         name = "test_issuer"
 147
 148     vl = verilog.convert(dut, ports=dut.external_ports(), name=name)
 149     with open(args.output_filename, "w") as f:
 150         f.write(vl)