src/soc/simple/test/test_microwatt.py

   1 from soc.simulator.program import Program
   2 from soc.fu.test.common import TestCase
   3
   4 import unittest
   5
   6 from nmigen import Module, Signal
   7 from nmigen.back.pysim import Simulator, Delay, Settle
   8 from nmutil.formaltest import FHDLTestCase
   9
  10 from soc.simple.issuer import TestIssuer
  11
  12 from soc.config.test.test_loadstore import TestMemPspec
  13 from soc.simple.test.test_core import (setup_regs, check_regs,
  14                                        wait_for_busy_clear,
  15                                        wait_for_busy_hi)
  16 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  17                                                  check_sim_memory)
  18
  19 from soc.simple.test.test_issuer import setup_i_memory
  20
  21 import sys
  22 sys.setrecursionlimit(10**6)
  23
  24
  25 class BinaryTestCase(FHDLTestCase):
  26     test_data = []
  27
  28     def __init__(self, name="general"):
  29         super().__init__(name)
  30         self.test_name = name
  31
  32     @unittest.skip("a bit big")
  33     def test_binary(self):
  34         with Program("1.bin") as program:
  35             self.run_tst_program(program)
  36
  37     def test_binary(self):
  38         with Program("hello_world.bin") as program:
  39             self.run_tst_program(program)
  40
  41     def run_tst_program(self, prog):
  42         initial_regs = [0] * 32
  43         tc = TestCase(prog, self.test_name, initial_regs, None, 0,
  44                                             None, 0,
  45                       do_sim=False)
  46         self.test_data.append(tc)
  47
  48
  49 class TestRunner(FHDLTestCase):
  50     def __init__(self, tst_data):
  51         super().__init__("binary_runner")
  52         self.test_data = tst_data
  53
  54     def binary_runner(self):
  55         m = Module()
  56         comb = m.d.comb
  57         go_insn_i = Signal()
  58         pc_i = Signal(32)
  59
  60         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  61                              imem_ifacetype='test_bare_wb',
  62                              addr_wid=48,
  63                              mask_wid=8,
  64                              reg_wid=64,
  65                              imem_test_depth=32768,
  66                              dmem_test_depth=32768)
  67         m.submodules.issuer = issuer = TestIssuer(pspec)
  68         imem = issuer.imem._get_memory()
  69         core = issuer.core
  70         pdecode2 = core.pdecode2
  71         l0 = core.l0
  72
  73         comb += issuer.pc_i.data.eq(pc_i)
  74         comb += issuer.go_insn_i.eq(go_insn_i)
  75
  76         # nmigen Simulation
  77         sim = Simulator(m)
  78         sim.add_clock(1e-6)
  79
  80         def process():
  81
  82             for test in self.test_data:
  83
  84                 # get core going
  85                 yield core.bigendian_i.eq(1)
  86                 yield core.core_start_i.eq(1)
  87                 yield
  88                 yield core.core_start_i.eq(0)
  89                 yield Settle()
  90
  91                 print(test.name)
  92                 program = test.program
  93                 self.subTest(test.name)
  94                 print ("regs", test.regs)
  95                 print ("sprs", test.sprs)
  96                 print ("cr", test.cr)
  97                 print ("mem", test.mem)
  98                 print ("msr", test.msr)
  99                 print ("assem", program.assembly)
 100                 instructions = list(program.generate_instructions())
 101
 102                 print ("instructions", len(instructions))
 103
 104                 pc = 0 # start of memory
 105
 106                 yield from setup_i_memory(imem, pc, instructions)
 107                 #yield from setup_test_memory(l0, sim)
 108                 yield from setup_regs(core, test)
 109
 110                 yield pc_i.eq(pc)
 111                 yield issuer.pc_i.ok.eq(1)
 112
 113                 while True:
 114
 115                     # start the instruction
 116                     yield go_insn_i.eq(1)
 117                     yield
 118                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
 119                     yield go_insn_i.eq(0)      # and don't issue a new insn
 120                     yield from wait_for_busy_hi(core)
 121                     yield Settle()
 122
 123                     # wait until executed
 124                     ins = yield core.raw_opcode_i
 125                     pc = yield issuer.pc_o
 126                     print("instruction: 0x%x @ %x" % (ins & 0xffffffff, pc))
 127                     yield from wait_for_busy_clear(core)
 128
 129                     terminated = yield core.core_terminated_o
 130                     print ("terminated", terminated)
 131
 132                     terminated = yield core.core_terminated_o
 133                     if terminated:
 134                         break
 135
 136             # register check
 137             #yield from check_regs(self, sim, core, test, code)
 138
 139             # Memory check
 140             #yield from check_sim_memory(self, l0, sim, code)
 141
 142         sim.add_sync_process(process)
 143         with sim.write_vcd("binary_issuer_simulator.vcd",
 144                             traces=[]):
 145             sim.run()
 146
 147
 148 if __name__ == "__main__":
 149     unittest.main(exit=False)
 150     suite = unittest.TestSuite()
 151     suite.addTest(TestRunner(BinaryTestCase.test_data))
 152
 153     runner = unittest.TextTestRunner()
 154     runner.run(suite)
 155