src/soc/simple/test/teststate.py

   1 from openpower.decoder.power_enums import XER_bits
   2
   3
   4 class SimState:
   5     def __init__(self, sim):
   6         self.sim = sim
   7
   8     def get_intregs(self):
   9         self.intregs = []
  10         for i in range(32):
  11             simregval = self.sim.gpr[i].asint()
  12             self.intregs.append(simregval)
  13
  14     def get_crregs(self):
  15         self.crregs = []
  16         for i in range(8):
  17             cri = self.sim.crl[7 - i].get_range().value
  18             self.crregs.append(cri)
  19
  20     def get_xregs(self):
  21         self.so = self.sim.spr['XER'][XER_bits['SO']].value
  22         self.ov = self.sim.spr['XER'][XER_bits['OV']].value
  23         self.ov32 = self.sim.spr['XER'][XER_bits['OV32']].value
  24         self.ca = self.sim.spr['XER'][XER_bits['CA']].value
  25         self.ca32 = self.sim.spr['XER'][XER_bits['CA32']].value
  26         self.ov = self.ov | (self.ov32 << 1)
  27         self.ca = self.ca | (self.ca32 << 1)
  28
  29     def get_pc(self):
  30         self.pc = self.sim.pc.CIA.value
  31
  32
  33 class HDLState:
  34     def __init__(self, core):
  35         self.core = core
  36
  37     def get_intregs(self):
  38         self.intregs = []
  39         for i in range(32):
  40             if self.core.regs.int.unary:
  41                 rval = yield self.core.regs.int.regs[i].reg
  42             else:
  43                 rval = yield self.core.regs.int.memory_array[i]
  44             self.intregs.append(rval)
  45         print("class core int regs", list(map(hex, intregs)))