3 This module implements the creation, inspection and comparison
4 of test states from different sources.
6 The basic premise is to create a test state using the TestState method.
7 The TestState method returns a test state object initialized with a
8 basic set of registers pulled from the 'to_test' object. The
9 state created can then be tested against other test states using the
12 The SimState class provides an example of needed registers and naming.
14 The TestState method relies on the 'state_factory' dictionary for lookup
15 of associated test class creation. The dictionary can be added to using
18 Also note when creating and accessing test state classes and object
19 methods, the use of yield from/yield is required.
25 from openpower
.decoder
.power_enums
import XER_bits
26 from openpower
.util
import log
30 yield from self
.get_intregs()
31 yield from self
.get_crregs()
32 yield from self
.get_xregs()
33 yield from self
.get_pc()
35 def compare(self
, s2
):
36 # Compare int registers
37 for i
, (self
.intregs
, s2
.intregs
) in enumerate(
38 zip(self
.intregs
, s2
.intregs
)):
39 log("asserting...reg", i
, self
.intregs
, s2
.intregs
)
40 log("code, frepr(code)", self
.code
, repr(self
.code
))
41 self
.dut
.assertEqual(self
.intregs
, s2
.intregs
,
42 "int reg %d (%s) not equal (%s) %s. got %x expected %x" %
43 (i
, self
.state_type
, s2
.state_type
, repr(self
.code
),
44 self
.intregs
, s2
.intregs
))
47 for i
, (self
.crregs
, s2
.crregs
) in enumerate(
48 zip(self
.crregs
, s2
.crregs
)):
49 log("asserting...cr", i
, self
.crregs
, s2
.crregs
)
50 self
.dut
.assertEqual(self
.crregs
, s2
.crregs
,
51 "cr reg %d (%s) not equal (%s) %s. got %x expected %x" %
52 (i
, self
.state_type
, s2
.state_type
, repr(self
.code
),
53 self
.crregs
, s2
.crregs
))
56 self
.dut
.assertEqual(self
.so
, s2
.so
, "so mismatch (%s != %s) %s" %
57 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
58 self
.dut
.assertEqual(self
.ov
, s2
.ov
, "ov mismatch (%s != %s) %s" %
59 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
60 self
.dut
.assertEqual(self
.ca
, s2
.ca
, "ca mismatch (%s != %s) %s" %
61 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
64 self
.dut
.assertEqual(self
.pc
, s2
.pc
, "pc mismatch (%s != %s) %s" %
65 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
68 class SimState(State
):
69 def __init__(self
, sim
):
72 def get_intregs(self
):
77 simregval
= self
.sim
.gpr
[i
].asint()
78 self
.intregs
.append(simregval
)
79 log("class sim int regs", list(map(hex, self
.intregs
)))
86 cri
= self
.sim
.crl
[7 - i
].get_range().value
87 self
.crregs
.append(cri
)
88 log("class sim cr regs", list(map(hex, self
.crregs
)))
94 self
.so
= self
.sim
.spr
['XER'][XER_bits
['SO']].value
95 self
.ov
= self
.sim
.spr
['XER'][XER_bits
['OV']].value
96 self
.ov32
= self
.sim
.spr
['XER'][XER_bits
['OV32']].value
97 self
.ca
= self
.sim
.spr
['XER'][XER_bits
['CA']].value
98 self
.ca32
= self
.sim
.spr
['XER'][XER_bits
['CA32']].value
99 self
.ov
= self
.ov |
(self
.ov32
<< 1)
100 self
.ca
= self
.ca |
(self
.ca32
<< 1)
101 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
102 log("class sim xregs", list(map(hex, self
.xregs
)))
108 self
.pc
= self
.sim
.pc
.CIA
.value
109 self
.pcl
.append(self
.pc
)
110 log("class sim pc", hex(self
.pc
))
113 class HDLState(State
):
114 def __init__(self
, core
):
117 def get_intregs(self
):
120 if self
.core
.regs
.int.unary
:
121 rval
= yield self
.core
.regs
.int.regs
[i
].reg
123 rval
= yield self
.core
.regs
.int.memory
._array
[i
]
124 self
.intregs
.append(rval
)
125 log("class hdl int regs", list(map(hex, self
.intregs
)))
127 def get_crregs(self
):
130 rval
= yield self
.core
.regs
.cr
.regs
[i
].reg
131 self
.crregs
.append(rval
)
132 log("class hdl cr regs", list(map(hex, self
.crregs
)))
136 self
.xr
= self
.core
.regs
.xer
137 self
.so
= yield self
.xr
.regs
[self
.xr
.SO
].reg
138 self
.ov
= yield self
.xr
.regs
[self
.xr
.OV
].reg
139 self
.ca
= yield self
.xr
.regs
[self
.xr
.CA
].reg
140 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
141 log("class hdl xregs", list(map(hex, self
.xregs
)))
145 self
.state
= self
.core
.regs
.state
146 self
.pc
= yield self
.state
.r_ports
['cia'].o_data
147 self
.pcl
.append(self
.pc
)
148 log("class hdl pc", hex(self
.pc
))
152 state_factory
= {'sim': SimState
, 'hdl': HDLState
}
157 state_factory
.update(sdic
)
160 def TestState(state_type
, to_test
, dut
, code
):
161 state_class
= state_factory
[state_type
]
162 state
= state_class(to_test
)
163 state
.to_test
= to_test
165 state
.state_type
= state_type
167 yield from state
.get_state()