1 from openpower
.decoder
.power_enums
import XER_bits
6 yield from self
.get_intregs()
7 yield from self
.get_crregs()
8 yield from self
.get_xregs()
9 yield from self
.get_pc()
12 class SimState(State
):
13 def __init__(self
, sim
):
16 def get_intregs(self
):
21 simregval
= self
.sim
.gpr
[i
].asint()
22 self
.intregs
.append(simregval
)
23 print("class sim int regs", list(map(hex, self
.intregs
)))
30 cri
= self
.sim
.crl
[7 - i
].get_range().value
31 self
.crregs
.append(cri
)
32 print("class sim cr regs", list(map(hex, self
.crregs
)))
38 self
.so
= self
.sim
.spr
['XER'][XER_bits
['SO']].value
39 self
.ov
= self
.sim
.spr
['XER'][XER_bits
['OV']].value
40 self
.ov32
= self
.sim
.spr
['XER'][XER_bits
['OV32']].value
41 self
.ca
= self
.sim
.spr
['XER'][XER_bits
['CA']].value
42 self
.ca32
= self
.sim
.spr
['XER'][XER_bits
['CA32']].value
43 self
.ov
= self
.ov |
(self
.ov32
<< 1)
44 self
.ca
= self
.ca |
(self
.ca32
<< 1)
45 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
46 print("class sim xregs", list(map(hex, self
.xregs
)))
52 self
.pc
= self
.sim
.pc
.CIA
.value
53 self
.pcl
.append(self
.pc
)
54 print("class sim pc", hex(self
.pc
))
57 class HDLState(State
):
58 def __init__(self
, core
):
61 def get_intregs(self
):
64 if self
.core
.regs
.int.unary
:
65 rval
= yield self
.core
.regs
.int.regs
[i
].reg
67 rval
= yield self
.core
.regs
.int.memory
._array
[i
]
68 self
.intregs
.append(rval
)
69 print("class hdl int regs", list(map(hex, self
.intregs
)))
74 rval
= yield self
.core
.regs
.cr
.regs
[i
].reg
75 self
.crregs
.append(rval
)
76 print("class hdl cr regs", list(map(hex, self
.crregs
)))
80 self
.xr
= self
.core
.regs
.xer
81 self
.so
= yield self
.xr
.regs
[self
.xr
.SO
].reg
82 self
.ov
= yield self
.xr
.regs
[self
.xr
.OV
].reg
83 self
.ca
= yield self
.xr
.regs
[self
.xr
.CA
].reg
84 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
85 print("class hdl xregs", list(map(hex, self
.xregs
)))
89 self
.state
= self
.core
.regs
.state
90 self
.pc
= yield self
.state
.r_ports
['cia'].o_data
91 self
.pcl
.append(self
.pc
)
92 print("class hdl pc", hex(self
.pc
))
95 def TestState(state_type
, dut
, state_dic
):
96 state_factory
= {'sim': SimState
, 'hdl': HDLState
}
97 state_class
= state_factory
[state_type
]
98 state
= state_class(state_dic
[state_type
])
100 state
.state_type
= state_type
101 yield from state
.get_state()