src/spec/simple_gpio.py

   1 """Simple GPIO peripheral on wishbone
   2
   3 This is an extremely simple GPIO peripheral intended for use in XICS
   4 testing, however it could also be used as an actual GPIO peripheral
   5
   6 Modified for use with pinmux, will probably change the class name later.
   7 """
   8 from random import randint
   9 from nmigen import Elaboratable, Module, Signal, Record, Array
  10 from nmigen.hdl.rec import Layout
  11 from nmigen.utils import log2_int
  12 from nmigen.cli import rtlil
  13 from soc.minerva.wishbone import make_wb_layout
  14 from nmutil.util import wrap
  15 from soc.bus.test.wb_rw import wb_read, wb_write
  16
  17 cxxsim = False
  18 if cxxsim:
  19     from nmigen.sim.cxxsim import Simulator, Settle
  20 else:
  21     from nmigen.sim import Simulator, Settle
  22
  23 # Layout of 8-bit configuration word:
  24 # bank_select[2:0] i/o | pden puen ien oe
  25 OESHIFT = 0
  26 IESHIFT = 1
  27 PUSHIFT = 2
  28 PDSHIFT = 3
  29 IOSHIFT = 4
  30 BANKSHIFT = 5
  31 NUMBANKBITS = 3 # only supporting 8 banks (0-7)
  32
  33 # For future testing:
  34 WORDSIZE = 8 # in bytes
  35
  36 class SimpleGPIO(Elaboratable):
  37
  38     def __init__(self, n_gpio=16):
  39         self.n_gpio = n_gpio
  40         class Spec: pass
  41         spec = Spec()
  42         spec.addr_wid = 30
  43         spec.mask_wid = 4
  44         spec.reg_wid = 32
  45         self.bus = Record(make_wb_layout(spec), name="gpio_wb")
  46
  47         self.bank_sel = Array([Signal(NUMBANKBITS) for _ in range(n_gpio)])
  48         self.gpio_o = Signal(n_gpio)
  49         self.gpio_oe = Signal(n_gpio)
  50         self.gpio_i = Signal(n_gpio)
  51         self.gpio_ie = Signal(n_gpio)
  52         self.pden = Signal(n_gpio)
  53         self.puen = Signal(n_gpio)
  54
  55         layout = (("oe", 1),
  56                   ("ie", 1),
  57                   ("puen", 1),
  58                   ("pden", 1),
  59                   ("io", 1),
  60                   ("bank_sel", NUMBANKBITS)
  61                  )
  62         self.csrbus = Record(layout)
  63
  64     def elaborate(self, platform):
  65         m = Module()
  66         comb, sync = m.d.comb, m.d.sync
  67
  68         bus = self.bus
  69         wb_rd_data = bus.dat_r
  70         wb_wr_data = bus.dat_w
  71         wb_ack = bus.ack
  72
  73         bank_sel = self.bank_sel
  74         gpio_o = self.gpio_o
  75         gpio_oe = self.gpio_oe
  76         gpio_i = self.gpio_i
  77         gpio_ie = self.gpio_ie
  78         pden = self.pden
  79         puen = self.puen
  80         csrbus = self.csrbus
  81
  82         comb += wb_ack.eq(0)
  83
  84         gpio_addr = Signal(log2_int(self.n_gpio))
  85         gpio_o_list = Array(list(gpio_o))
  86         print(bank_sel)
  87         print(gpio_o_list)
  88         gpio_oe_list = Array(list(gpio_oe))
  89         gpio_i_list = Array(list(gpio_i))
  90         gpio_ie_list = Array(list(gpio_ie))
  91         pden_list = Array(list(pden))
  92         puen_list = Array(list(puen))
  93
  94         #print("Types:")
  95         #print("gpio_addr: ", type(gpio_addr))
  96         #print("gpio_o_list: ", type(gpio_o_list))
  97         #print("bank_sel: ", type(bank_sel))
  98
  99         # One address used to configure CSR, set output, read input
 100         with m.If(bus.cyc & bus.stb):
 101             comb += wb_ack.eq(1) # always ack
 102             comb += gpio_addr.eq(bus.adr)
 103             with m.If(bus.we): # write
 104                 # Configure CSR
 105                 sync += csrbus.eq(wb_wr_data)
 106                 sync += gpio_oe_list[gpio_addr].eq(csrbus.oe)
 107                 sync += gpio_ie_list[gpio_addr].eq(csrbus.ie)
 108                 # check GPIO is in output mode and NOT input (oe high, ie low)
 109                 with m.If(csrbus.oe & (~csrbus.ie)):
 110                     sync += gpio_o_list[gpio_addr].eq(csrbus.io)
 111                 sync += puen_list[gpio_addr].eq(csrbus.puen)
 112                 sync += pden_list[gpio_addr].eq(csrbus.pden)
 113                 # TODO: clean up name
 114                 sync += bank_sel[gpio_addr].eq(csrbus.bank_sel)
 115             with m.Else(): # read
 116                 # Read the state of CSR bits
 117                 # Return state of input if ie
 118                 with m.If(gpio_ie_list[gpio_addr] == 1):
 119                     sync += csrbus.io.eq(gpio_i_list[gpio_addr])
 120                     comb += wb_rd_data.eq(csrbus)
 121                 # Return state of out if oe
 122                 with m.Else():
 123                     sync += csrbus.io.eq(gpio_o_list[gpio_addr])
 124                     comb += wb_rd_data.eq(csrbus)
 125         return m
 126
 127     def __iter__(self):
 128         for field in self.bus.fields.values():
 129             yield field
 130         yield self.gpio_o
 131
 132     def ports(self):
 133         return list(self)
 134
 135 # TODO: probably make into class (or return state in a variable)
 136 def gpio_configure(dut, gpio, oe, ie, puen, pden, outval, bank_sel):
 137     csr_val = ( (oe   << OESHIFT)
 138               | (ie   << IESHIFT)
 139               | (puen << PUSHIFT)
 140               | (pden << PDSHIFT)
 141               | (bank_sel << BANKSHIFT) )
 142     print("Configuring CSR to {0:x}".format(csr_val))
 143     yield from wb_write(dut.bus, gpio, csr_val)
 144     return csr_val # return the config state
 145
 146 # TODO: Return the configuration states
 147 def gpio_rd_csr(dut, gpio):
 148     csr_val = yield from wb_read(dut.bus, gpio)
 149     print("GPIO{0} | CSR: {1:x}".format(gpio, csr_val))
 150     print("Output Enable: {0:b}".format((csr_val >> OESHIFT) & 1))
 151     print("Input Enable: {0:b}".format((csr_val >> IESHIFT) & 1))
 152     print("Pull-Up Enable: {0:b}".format((csr_val >> PUSHIFT) & 1))
 153     print("Pull-Down Enable: {0:b}".format((csr_val >> PDSHIFT) & 1))
 154     if ((csr_val >> IESHIFT) & 1):
 155         print("Input: {0:b}".format((csr_val >> IOSHIFT) & 1))
 156     else:
 157         print("Output: {0:b}".format((csr_val >> IOSHIFT) & 1))
 158     print("Bank Select: {0:b}".format((csr_val >> BANKSHIFT) & 1))
 159     # gpio_parse_csr(csr_val)
 160     return csr_val
 161
 162 # TODO
 163 def gpio_rd_input(dut, gpio):
 164     in_val = yield from wb_read(dut.bus, gpio)
 165     in_val = (in_val >> IOSHIFT) & 1
 166     print("GPIO{0} | Input: {1:b}".format(gpio, in_val))
 167     return in_val
 168
 169 def gpio_set_out(dut, gpio, csr_val, output):
 170     print("Setting GPIO{0} output to {1}".format(gpio, output))
 171     yield from wb_write(dut.bus, gpio, csr_val | (output<<IOSHIFT))
 172
 173 # TODO: There's probably a cleaner way to clear the bit...
 174 def gpio_set_in_pad(dut, gpio, in_val):
 175     old_in_val = yield dut.gpio_i
 176     if in_val:
 177         new_in_val = old_in_val | (in_val << gpio)
 178     else:
 179         temp = (old_in_val >> gpio) & 1
 180         if temp:
 181             mask = ~(1 << gpio)
 182             new_in_val = old_in_val & mask
 183         else:
 184             new_in_val = old_in_val
 185     print("Previous GPIO i: {0:b} | New GPIO i: {1:b}"
 186           .format(old_in_val, new_in_val))
 187     yield dut.gpio_i.eq(new_in_val)
 188
 189 def gpio_test_in_pattern(dut, pattern):
 190     num_gpios = len(dut.gpio_o)
 191     print("Test pattern:")
 192     print(pattern)
 193     for pat in range(0, len(pattern)):
 194         for gpio in range(0, num_gpios):
 195             yield from gpio_set_in_pad(dut, gpio, pattern[pat])
 196             yield
 197             temp = yield from gpio_rd_input(dut, gpio)
 198             print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
 199             assert (temp == pattern[pat])
 200             pat += 1
 201             if pat == len(pattern):
 202                 break
 203
 204
 205 def sim_gpio(dut, use_random=True):
 206     print(dir(dut))
 207     print(dut)
 208     num_gpios = len(dut.gpio_o)
 209     if use_random:
 210         bank_sel = randint(0, 2**NUMBANKBITS)
 211         print("Random bank_select: {0:b}".format(bank_sel))
 212     else:
 213         bank_sel = 0 #3 # not special, chose for testing
 214     oe = 1
 215     ie = 0
 216     output = 0
 217     puen = 0 # 1
 218     pden = 0
 219     gpio_csr = [0] * num_gpios
 220     # Configure GPIOs for
 221     for gpio in range(0, 1): #num_gpios):
 222         gpio_csr[gpio] = yield from gpio_configure(dut, gpio, oe, ie, puen,
 223                                                    pden, output, bank_sel)
 224     # Set outputs
 225     for gpio in range(0, 1): #num_gpios):
 226         yield from gpio_set_out(dut, gpio, gpio_csr[gpio], 1)
 227
 228     # Read CSR
 229     for gpio in range(0, 1): #num_gpios):
 230         yield from gpio_rd_csr(dut, gpio)
 231
 232     # Configure for input
 233     oe = 0
 234     ie = 1
 235     gpio_csr[0] = yield from gpio_configure(dut, 0, oe, ie, puen,
 236                                             pden, output, bank_sel)
 237     # Input testing
 238     yield from gpio_set_in_pad(dut, 0, 1)
 239     yield
 240     temp = yield from gpio_rd_input(dut, 0)
 241
 242
 243     # TODO: not working yet
 244     #test_pattern = []
 245     #for i in range(0, (num_gpios * 2)):
 246     #    test_pattern.append(randint(0,1))
 247     #yield from gpio_test_in_pattern(dut, test_pattern)
 248
 249     print("Finished the simple GPIO block test!")
 250
 251 def test_gpio():
 252     dut = SimpleGPIO()
 253     vl = rtlil.convert(dut, ports=dut.ports())
 254     with open("test_gpio.il", "w") as f:
 255         f.write(vl)
 256
 257     m = Module()
 258     m.submodules.xics_icp = dut
 259
 260     sim = Simulator(m)
 261     sim.add_clock(1e-6)
 262
 263     sim.add_sync_process(wrap(sim_gpio(dut, use_random=False)))
 264     sim_writer = sim.write_vcd('test_gpio.vcd')
 265     with sim_writer:
 266         sim.run()
 267
 268
 269 if __name__ == '__main__':
 270     test_gpio()
 271