src/spec/testing.py

   1 try:
   2     from UserDict import UserDict
   3 except ImportError:
   4     from collections import UserDict
   5
   6
   7 class Wire(object):
   8     """ a wire which can be hi, lo or tri-state
   9     """
  10
  11     def __init__(self, wires, name):
  12         self.wires = wires
  13         self.wires[name] = self
  14         self.name = name
  15         self.val = 'x'
  16
  17
  18 class TestPin(object):
  19     """ a test pin can be an output, input or in-out
  20         and it stores the state in an associated wire
  21     """
  22
  23
  24 class Wires(UserDict):
  25     """ a set of wires
  26     """
  27
  28     def __init__(self):
  29         UserDict.__init__(self)
  30
  31
  32 def dummytest(ps, output_dir, output_type):
  33     print (ps, output_dir, output_type)
  34     print (dir(ps))
  35     print (ps.fnspec)
  36
  37     # basically we need to replicate the entirety of the
  38     # verilog module's inputs and outputs, so that we can
  39     # set inputs hi/lo and then test expected outputs hi/lo.
  40     # so, set up some wires by going through the interfaces
  41     w = Wires()