3 pinmux documented here https://libre-soc.org/docs/pinmux/
5 from nmigen
.build
.dsl
import Resource
, Subsignal
, Pins
6 from nmigen
.build
.plat
import TemplatedPlatform
7 from nmigen
.build
.res
import ResourceManager
, ResourceError
8 from nmigen
.hdl
.rec
import Layout
9 from nmigen
import Elaboratable
, Signal
, Module
, Instance
10 from collections
import OrderedDict
11 from jtag
import JTAG
, resiotypes
12 from copy
import deepcopy
13 from nmigen
.cli
import rtlil
16 # extra dependencies for jtag testing (?)
17 #from soc.bus.sram import SRAM
19 #from nmigen import Memory
20 from nmigen
.sim
import Simulator
, Delay
, Settle
, Tick
, Passive
22 from nmutil
.util
import wrap
24 # from soc.debug.jtagutils import (jtag_read_write_reg,
25 # jtag_srv, jtag_set_reset,
26 # jtag_set_ir, jtag_set_get_dr)
28 from soc
.debug
.test
.test_jtag_tap
import (jtag_read_write_reg
,
35 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
36 from c4m
.nmigen
.jtag
.bus
import Interface
as JTAGInterface
37 from soc
.debug
.dmi
import DMIInterface
, DBGCore
38 #from soc.debug.test.dmi_sim import dmi_sim
39 #from soc.debug.test.jtagremote import JTAGServer, JTAGClient
40 from nmigen
.build
.res
import ResourceError
42 # Was thinking of using these functions, but skipped for simplicity for now
43 # XXX nope. the output from JSON file.
44 # from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
45 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
46 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
48 # File for stage 1 pinmux tested proposed by Luke,
49 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
53 # sigh this needs to come from pinmux.
56 gpios
.append("%d*" % i
)
57 return {'uart': ['tx+', 'rx-'],
59 # 'jtag': ['tms-', 'tdi-', 'tdo+', 'tck+'],
60 'i2c': ['sda*', 'scl+']}
64 a function is needed which turns the results of dummy_pinset()
67 [UARTResource("uart", 0, tx=..., rx=..),
68 I2CResource("i2c", 0, scl=..., sda=...),
69 Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
70 Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
76 def create_resources(pinset
):
78 for periph
, pins
in pinset
.items():
81 #print("I2C required!")
82 resources
.append(I2CResource('i2c', 0, sda
='sda', scl
='scl'))
83 elif periph
== 'uart':
84 #print("UART required!")
85 resources
.append(UARTResource('uart', 0, tx
='tx', rx
='rx'))
86 elif periph
== 'gpio':
87 #print("GPIO required!")
88 print("GPIO is defined as '*' type, meaning i, o and oe needed")
91 pname
= "gpio"+pin
[:-1] # strip "*" on end
92 # urrrr... tristsate and io assume a single pin which is
93 # of course exactly what we don't want in an ASIC: we want
94 # *all three* pins but the damn port is not outputted
95 # as a triplet, it's a single Record named "io". sigh.
96 # therefore the only way to get a triplet of i/o/oe
97 # is to *actually* create explicit triple pins
98 # XXX ARRRGH, doesn't work
99 # pad = Subsignal("io",
100 # Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
101 # dir="io", assert_width=3))
102 #ios.append(Resource(pname, 0, pad))
104 pads
.append(Subsignal("i",
105 Pins(pname
+"_i", dir="i", assert_width
=1)))
106 pads
.append(Subsignal("o",
107 Pins(pname
+"_o", dir="o", assert_width
=1)))
108 pads
.append(Subsignal("oe",
109 Pins(pname
+"_oe", dir="o", assert_width
=1)))
110 ios
.append(Resource
.family(pname
, 0, default_name
=pname
,
112 resources
.append(Resource
.family(periph
, 0, default_name
="gpio",
115 # add clock and reset
116 clk
= Resource("clk", 0, Pins("sys_clk", dir="i"))
117 rst
= Resource("rst", 0, Pins("sys_rst", dir="i"))
118 resources
.append(clk
)
119 resources
.append(rst
)
123 def JTAGResource(*args
):
125 io
.append(Subsignal("tms", Pins("tms", dir="i", assert_width
=1)))
126 io
.append(Subsignal("tdi", Pins("tdi", dir="i", assert_width
=1)))
127 io
.append(Subsignal("tck", Pins("tck", dir="i", assert_width
=1)))
128 io
.append(Subsignal("tdo", Pins("tdo", dir="o", assert_width
=1)))
129 return Resource
.family(*args
, default_name
="jtag", ios
=io
)
132 def UARTResource(*args
, rx
, tx
):
134 io
.append(Subsignal("rx", Pins(rx
, dir="i", assert_width
=1)))
135 io
.append(Subsignal("tx", Pins(tx
, dir="o", assert_width
=1)))
136 return Resource
.family(*args
, default_name
="uart", ios
=io
)
139 def I2CResource(*args
, scl
, sda
):
142 pads
.append(Subsignal("i", Pins(sda
+"_i", dir="i", assert_width
=1)))
143 pads
.append(Subsignal("o", Pins(sda
+"_o", dir="o", assert_width
=1)))
144 pads
.append(Subsignal("oe", Pins(sda
+"_oe", dir="o", assert_width
=1)))
145 ios
.append(Resource
.family(sda
, 0, default_name
=sda
, ios
=pads
))
147 pads
.append(Subsignal("i", Pins(scl
+"_i", dir="i", assert_width
=1)))
148 pads
.append(Subsignal("o", Pins(scl
+"_o", dir="o", assert_width
=1)))
149 pads
.append(Subsignal("oe", Pins(scl
+"_oe", dir="o", assert_width
=1)))
150 ios
.append(Resource
.family(scl
, 0, default_name
=scl
, ios
=pads
))
151 return Resource
.family(*args
, default_name
="i2c", ios
=ios
)
154 # top-level demo module.
155 class Blinker(Elaboratable
):
156 def __init__(self
, pinset
, resources
, no_jtag_connect
=False):
157 self
.no_jtag_connect
= no_jtag_connect
158 self
.jtag
= JTAG({}, "sync", resources
=resources
)
159 #memory = Memory(width=32, depth=16)
160 #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
162 def elaborate(self
, platform
):
163 jtag_resources
= self
.jtag
.pad_mgr
.resources
165 m
.submodules
.jtag
= self
.jtag
166 #m.submodules.sram = self.sram
169 #m.d.sync += count.eq(count+1)
170 print("resources", platform
, jtag_resources
.items())
171 gpio
= self
.jtag
.request('gpio')
172 print(gpio
, gpio
.layout
, gpio
.fields
)
173 # get the GPIO bank, mess about with some of the pins
174 #m.d.comb += gpio.gpio0.o.eq(1)
175 #m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
176 #m.d.comb += gpio.gpio1.oe.eq(count[4])
177 #m.d.sync += count[0].eq(gpio.gpio1.i)
180 gpio_i_ro
= Signal(num_gpios
)
181 gpio_o_test
= Signal(num_gpios
)
182 gpio_oe_test
= Signal(num_gpios
)
184 # Create a read-only copy of core-side GPIO input signals
185 # for Simulation asserts
186 m
.d
.comb
+= gpio_i_ro
[0].eq(gpio
.gpio0
.i
)
187 m
.d
.comb
+= gpio_i_ro
[1].eq(gpio
.gpio1
.i
)
188 m
.d
.comb
+= gpio_i_ro
[2].eq(gpio
.gpio2
.i
)
189 m
.d
.comb
+= gpio_i_ro
[3].eq(gpio
.gpio3
.i
)
191 # Wire up the output signal of each gpio by XOR'ing each bit of
192 # gpio_o_test with gpio's input
193 # Wire up each bit of gpio_oe_test signal to oe signal of each gpio.
194 # Turn into a loop at some point, probably a way without
196 m
.d
.comb
+= gpio
.gpio0
.o
.eq(gpio_o_test
[0] ^ gpio
.gpio0
.i
)
197 m
.d
.comb
+= gpio
.gpio1
.o
.eq(gpio_o_test
[1] ^ gpio
.gpio1
.i
)
198 m
.d
.comb
+= gpio
.gpio2
.o
.eq(gpio_o_test
[2] ^ gpio
.gpio2
.i
)
199 m
.d
.comb
+= gpio
.gpio3
.o
.eq(gpio_o_test
[3] ^ gpio
.gpio3
.i
)
201 m
.d
.comb
+= gpio
.gpio0
.oe
.eq(gpio_oe_test
[0])
202 m
.d
.comb
+= gpio
.gpio1
.oe
.eq(gpio_oe_test
[1])
203 m
.d
.comb
+= gpio
.gpio2
.oe
.eq(gpio_oe_test
[2])
204 m
.d
.comb
+= gpio
.gpio3
.oe
.eq(gpio_oe_test
[3])
206 # get the UART resource, mess with the output tx
207 uart
= self
.jtag
.request('uart')
208 print("uart fields", uart
, uart
.fields
)
209 self
.uart_tx_test
= Signal()
210 #self.intermediary = Signal()
211 #m.d.comb += uart.tx.eq(self.intermediary)
212 #m.d.comb += self.intermediary.eq(uart.rx)
213 # Allow tx to be controlled externally
214 m
.d
.comb
+= uart
.tx
.eq(self
.uart_tx_test ^ uart
.rx
)
218 i2c_sda_oe_test
= Signal(num_i2c
)
219 i2c_scl_oe_test
= Signal(num_i2c
)
220 i2c
= self
.jtag
.request('i2c')
221 print("i2c fields", i2c
, i2c
.fields
)
222 # Connect in loopback
223 m
.d
.comb
+= i2c
.scl
.o
.eq(i2c
.scl
.i
)
224 m
.d
.comb
+= i2c
.sda
.o
.eq(i2c
.sda
.i
)
225 # Connect output enable to test port for sim
226 m
.d
.comb
+= i2c
.sda
.oe
.eq(i2c_sda_oe_test
)
227 m
.d
.comb
+= i2c
.scl
.oe
.eq(i2c_scl_oe_test
)
229 # to even be able to get at objects, you first have to make them
230 # available - i.e. not as local variables
231 # Public attributes are equivalent to input/output ports in hdl's
236 self
.i2c_sda_oe_test
= i2c_sda_oe_test
237 self
.i2c_scl_oe_test
= i2c_scl_oe_test
238 self
.gpio_i_ro
= gpio_i_ro
239 self
.gpio_o_test
= gpio_o_test
240 self
.gpio_oe_test
= gpio_oe_test
242 # sigh these wire up to the pads so you cannot set Signals
243 # that are already wired
244 if self
.no_jtag_connect
: # bypass jtag pad connect for testing purposes
246 return self
.jtag
.boundary_elaborate(m
, platform
)
252 yield from self
.jtag
.iter_ports()
256 _trellis_command_templates = [
258 {{invoke_tool("yosys")}}
260 {{get_override("yosys_opts")|options}}
267 # sigh, have to create a dummy platform for now.
268 # TODO: investigate how the heck to get it to output ilang. or verilog.
269 # or, anything, really. but at least it doesn't barf
272 class ASICPlatform(TemplatedPlatform
):
274 resources
= OrderedDict()
276 command_templates
= ['/bin/true'] # no command needed: stops barfing
278 **TemplatedPlatform
.build_script_templates
,
283 "{{name}}.debug.v": r
"""
284 /* {{autogenerated}} */
285 {{emit_debug_verilog()}}
289 default_clk
= "clk" # should be picked up / overridden by platform sys.clk
290 default_rst
= "rst" # should be picked up / overridden by platform sys.rst
292 def __init__(self
, resources
, jtag
):
296 # create set of pin resources based on the pinset, this is for the core
297 #jtag_resources = self.jtag.pad_mgr.resources
298 self
.add_resources(resources
)
300 # add JTAG without scan
301 self
.add_resources([JTAGResource('jtag', 0)], no_boundary_scan
=True)
303 def add_resources(self
, resources
, no_boundary_scan
=False):
304 print("ASICPlatform add_resources", resources
)
305 return super().add_resources(resources
)
307 # def iter_ports(self):
308 # yield from super().iter_ports()
309 # for io in self.jtag.ios.values():
310 # print ("iter ports", io.layout, io)
311 # for field in io.core.fields:
312 # yield getattr(io.core, field)
313 # for field in io.pad.fields:
314 # yield getattr(io.pad, field)
316 # XXX these aren't strictly necessary right now but the next
317 # phase is to add JTAG Boundary Scan so it maaay be worth adding?
318 # at least for the print statements
319 def get_input(self
, pin
, port
, attrs
, invert
):
320 self
._check
_feature
("single-ended input", pin
, attrs
,
321 valid_xdrs
=(0,), valid_attrs
=None)
324 print(" get_input", pin
, "port", port
, port
.layout
)
325 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
328 def get_output(self
, pin
, port
, attrs
, invert
):
329 self
._check
_feature
("single-ended output", pin
, attrs
,
330 valid_xdrs
=(0,), valid_attrs
=None)
333 print(" get_output", pin
, "port", port
, port
.layout
)
334 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, pin
.o
))
337 def get_tristate(self
, pin
, port
, attrs
, invert
):
338 self
._check
_feature
("single-ended tristate", pin
, attrs
,
339 valid_xdrs
=(0,), valid_attrs
=None)
341 print(" get_tristate", pin
, "port", port
, port
.layout
)
343 print(" pad", pin
, port
, attrs
)
344 print(" pin", pin
.layout
)
346 # m.submodules += Instance("$tribuf",
349 # i_A=self._invert_if(invert, pin.o),
352 m
.d
.comb
+= io
.core
.o
.eq(pin
.o
)
353 m
.d
.comb
+= io
.core
.oe
.eq(pin
.oe
)
354 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
355 m
.d
.comb
+= io
.pad
.i
.eq(port
.i
)
356 m
.d
.comb
+= port
.o
.eq(io
.pad
.o
)
357 m
.d
.comb
+= port
.oe
.eq(io
.pad
.oe
)
360 def get_input_output(self
, pin
, port
, attrs
, invert
):
361 self
._check
_feature
("single-ended input/output", pin
, attrs
,
362 valid_xdrs
=(0,), valid_attrs
=None)
364 print(" get_input_output", pin
, "port", port
, port
.layout
)
366 print(" port layout", port
.layout
)
368 print(" layout", pin
.layout
)
369 # m.submodules += Instance("$tribuf",
372 # i_A=self._invert_if(invert, io.pad.o),
375 # Create aliases for the port sub-signals
380 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port_i
))
381 m
.d
.comb
+= port_o
.eq(self
._invert
_if
(invert
, pin
.o
))
382 m
.d
.comb
+= port_oe
.eq(pin
.oe
)
386 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
387 """override toolchain_prepare in order to grab the fragment
389 self
.fragment
= fragment
390 return super().toolchain_prepare(fragment
, name
, **kwargs
)
394 print("Starting sanity test case!")
395 print("printing out list of stuff in top")
396 print("JTAG IOs", top
.jtag
.ios
)
397 # ok top now has a variable named "gpio", let's enumerate that too
398 print("printing out list of stuff in top.gpio and its type")
399 print(top
.gpio
.__class
__.__name
__, dir(top
.gpio
))
400 # ok, it's a nmigen Record, therefore it has a layout. let's print
402 print("top.gpio is a Record therefore has fields and a layout")
403 print(" layout:", top
.gpio
.layout
)
404 print(" fields:", top
.gpio
.fields
)
405 print("Fun never ends...")
406 print(" layout, gpio2:", top
.gpio
.layout
['gpio2'])
407 print(" fields, gpio2:", top
.gpio
.fields
['gpio2'])
408 print(top
.jtag
.__class
__.__name
__, dir(top
.jtag
))
410 print(top
.jtag
.resource_table_pads
[('gpio', 0)])
412 # etc etc. you get the general idea
414 yield top
.uart
.rx
.eq(0)
415 yield Delay(delayVal
)
417 yield top
.gpio
.gpio2
.o
.eq(0)
418 yield top
.gpio
.gpio3
.o
.eq(1)
420 yield top
.gpio
.gpio3
.oe
.eq(1)
422 yield top
.gpio
.gpio3
.oe
.eq(0)
423 # grab the JTAG resource pad
424 gpios_pad
= top
.jtag
.resource_table_pads
[('gpio', 0)]
425 yield gpios_pad
.gpio3
.i
.eq(1)
426 yield Delay(delayVal
)
428 yield top
.gpio
.gpio2
.oe
.eq(1)
429 yield top
.gpio
.gpio3
.oe
.eq(1)
430 yield gpios_pad
.gpio3
.i
.eq(0)
431 yield top
.jtag
.gpio
.gpio2
.i
.eq(1)
432 yield Delay(delayVal
)
436 # get a value first (as an integer). you were trying to set
437 # it to the actual Signal. this is not going to work. or if
438 # it does, it's very scary.
439 gpio_o2
= not gpio_o2
440 yield top
.gpio
.gpio2
.o
.eq(gpio_o2
)
442 # ditto: here you are trying to set to an AST expression
443 # which is inadviseable (likely to fail)
444 gpio_o3
= not gpio_o2
445 yield top
.gpio
.gpio3
.o
.eq(gpio_o3
)
446 yield Delay(delayVal
)
448 # grab the JTAG resource pad
449 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
450 yield uart_pad
.rx
.i
.eq(gpio_o2
)
451 yield Delay(delayVal
)
453 yield # one clock cycle
454 tx_val
= yield uart_pad
.tx
.o
455 print("xmit uart", tx_val
, gpio_o2
)
457 print("jtag pad table keys")
458 print(top
.jtag
.resource_table_pads
.keys())
459 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
460 print("uart pad", uart_pad
)
461 print("uart pad", uart_pad
.layout
)
463 yield top
.gpio
.gpio2
.oe
.eq(0)
464 yield top
.gpio
.gpio3
.oe
.eq(0)
465 yield top
.jtag
.gpio
.gpio2
.i
.eq(0)
466 yield Delay(delayVal
)
471 print("Starting GPIO test case!")
472 # TODO: make pad access parametrisable to cope with more than 4 GPIOs
473 num_gpios
= dut
.gpio_o_test
.width
474 # Grab GPIO outpud pad resource from JTAG BS - end of chain
475 print(dut
.jtag
.boundary_scan_pads
.keys())
476 gpio0_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio0__o']['o']
477 gpio1_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio1__o']['o']
478 gpio2_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio2__o']['o']
479 gpio3_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio3__o']['o']
480 gpio_pad_out
= [gpio0_o
, gpio1_o
, gpio2_o
, gpio3_o
]
482 # Grab GPIO output enable pad resource from JTAG BS - end of chain
483 gpio0_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio0__oe']['o']
484 gpio1_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio1__oe']['o']
485 gpio2_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio2__oe']['o']
486 gpio3_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio3__oe']['o']
487 gpio_pad_oe
= [gpio0_oe
, gpio1_oe
, gpio2_oe
, gpio3_oe
]
489 # Grab GPIO input pad resource from JTAG BS - start of chain
490 gpio0_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio0__i']['i']
491 gpio1_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio1__i']['i']
492 gpio2_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio2__i']['i']
493 gpio3_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio3__i']['i']
494 gpio_pad_in
= [gpio0_pad_in
, gpio1_pad_in
, gpio2_pad_in
, gpio3_pad_in
]
496 # Have the sim run through a for-loop where the gpio_o_test is
497 # incremented like a counter (0000, 0001...)
498 # At each iteration of the for-loop, assert:
499 # + output set at core matches output seen at pad
500 # TODO + input set at pad matches input seen at core
501 # TODO + if gpio_o_test bit is cleared, output seen at pad matches
503 num_gpio_o_states
= num_gpios
**2
504 pad_out
= [0] * num_gpios
505 pad_oe
= [0] * num_gpios
506 #print("Num of permutations of gpio_o_test record: ", num_gpio_o_states)
507 for gpio_o_val
in range(0, num_gpio_o_states
):
508 yield dut
.gpio_o_test
.eq(gpio_o_val
)
510 yield # Move to the next clk cycle
512 # Cycle through all input combinations
513 for gpio_i_val
in range(0, num_gpio_o_states
):
514 # Set each gpio input at pad to test value
515 for gpio_bit
in range(0, num_gpios
):
516 yield gpio_pad_in
[gpio_bit
].eq((gpio_i_val
>> gpio_bit
) & 0x1)
518 # After changing the gpio0/1/2/3 inputs,
519 # the output is also going to change.
520 # *therefore it must be read again* to get the
521 # snapshot (as a python value)
522 for gpio_bit
in range(0, num_gpios
):
523 pad_out
[gpio_bit
] = yield gpio_pad_out
[gpio_bit
]
525 for gpio_bit
in range(0, num_gpios
):
526 # check core and pad in
527 gpio_i_ro
= yield dut
.gpio_i_ro
[gpio_bit
]
528 out_test_bit
= ((gpio_o_val
& (1 << gpio_bit
)) != 0)
529 in_bit
= ((gpio_i_val
& (1 << gpio_bit
)) != 0)
530 # Check that the core end input matches pad
531 assert in_bit
== gpio_i_ro
532 # Test that the output at pad matches:
533 # Pad output == given test output XOR test input
534 assert (out_test_bit ^ in_bit
) == pad_out
[gpio_bit
]
536 # For debugging - VERY verbose
537 # print("---------------------")
538 #print("Test Out: ", bin(gpio_o_val))
539 #print("Test Input: ", bin(gpio_i_val))
541 #print("Pad Output: ", list(reversed(pad_out)))
542 # print("---------------------")
544 # For-loop for testing output enable signals
545 for gpio_o_val
in range(0, num_gpio_o_states
):
546 yield dut
.gpio_oe_test
.eq(gpio_o_val
)
547 yield # Move to the next clk cycle
549 for gpio_bit
in range(0, num_gpios
):
550 pad_oe
[gpio_bit
] = yield gpio_pad_oe
[gpio_bit
]
553 for gpio_bit
in range(0, num_gpios
):
554 oe_test_bit
= ((gpio_o_val
& (1 << gpio_bit
)) != 0)
555 # oe set at core matches oe seen at pad:
556 assert oe_test_bit
== pad_oe
[gpio_bit
]
557 # For debugging - VERY verbose
558 # print("---------------------")
559 #print("Test Output Enable: ", bin(gpio_o_val))
561 #print("Pad Output Enable: ", list(reversed(pad_oe)))
562 # print("---------------------")
564 # Reset test ouput register
565 yield dut
.gpio_o_test
.eq(0)
566 print("GPIO Test PASSED!")
570 # grab the JTAG resource pad
572 print("bs pad keys", dut
.jtag
.boundary_scan_pads
.keys())
574 uart_rx_pad
= dut
.jtag
.boundary_scan_pads
['uart_0__rx']['i']
575 uart_tx_pad
= dut
.jtag
.boundary_scan_pads
['uart_0__tx']['o']
577 print("uart rx pad", uart_rx_pad
)
578 print("uart tx pad", uart_tx_pad
)
580 # Test UART by writing 0 and 1 to RX
581 # Internally TX connected to RX,
582 # so match pad TX with RX
583 for i
in range(0, 2):
584 yield uart_rx_pad
.eq(i
)
585 # yield uart_rx_pad.eq(i)
587 yield # one clock cycle
588 tx_val
= yield uart_tx_pad
589 print("xmit uart", tx_val
, 1)
592 print("UART Test PASSED!")
596 i2c_sda_i_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__sda__i']['i']
597 i2c_sda_o_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__sda__o']['o']
598 i2c_sda_oe_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__sda__oe']['o']
600 i2c_scl_i_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__scl__i']['i']
601 i2c_scl_o_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__scl__o']['o']
602 i2c_scl_oe_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__scl__oe']['o']
604 #i2c_pad = dut.jtag.resource_table_pads[('i2c', 0)]
605 #print ("i2c pad", i2c_pad)
606 #print ("i2c pad", i2c_pad.layout)
608 for i
in range(0, 2):
609 yield i2c_sda_i_pad
.eq(i
) # i2c_pad.sda.i.eq(i)
610 yield i2c_scl_i_pad
.eq(i
) # i2c_pad.scl.i.eq(i)
611 yield dut
.i2c_sda_oe_test
.eq(i
)
612 yield dut
.i2c_scl_oe_test
.eq(i
)
614 yield # one clock cycle
615 sda_o_val
= yield i2c_sda_o_pad
616 scl_o_val
= yield i2c_scl_o_pad
617 sda_oe_val
= yield i2c_sda_oe_pad
618 scl_oe_val
= yield i2c_scl_oe_pad
619 print("Test input: ", i
, " SDA/SCL out: ", sda_o_val
, scl_o_val
,
620 " SDA/SCL oe: ", sda_oe_val
, scl_oe_val
)
621 assert sda_o_val
== i
622 assert scl_o_val
== i
623 assert sda_oe_val
== i
624 assert scl_oe_val
== i
626 print("I2C Test PASSED!")
629 # JTAG boundary scan reg addresses - See c4m/nmigen/jtag/tap.py line #357
636 def test_jtag_bs_chain(dut
):
640 print("JTAG BS Reset")
641 yield from jtag_set_reset(dut
.jtag
)
643 #print("JTAG I/O dictionary of core/pad signals:")
644 # print(dut.jtag.ios.keys())
646 # Based on number of ios entries, produce a test shift reg pattern
647 bslen
= len(dut
.jtag
.ios
)
648 bsdata
= 2**bslen
- 1 # Fill with all 1s for now
649 fulldata
= bsdata
# for testing
650 emptydata
= 0 # for testing
652 mask_inputs
= produce_ios_io_mask(dut
, is_input
=True)
653 mask_outputs
= produce_ios_io_mask(dut
, is_input
=False)
657 # TODO: make format based on bslen, not a magic number 20-bits wide
658 print("Input Mask: {0:020b}".format(mask_inputs
))
659 print("Output Mask: {0:020b}".format(mask_outputs
))
661 print(dut
.jtag
._ir
_width
)
665 uart_rx_pad
= dut
.jtag
.boundary_scan_pads
['uart_0__rx']['i']
666 yield uart_rx_pad
.eq(1)
667 yield from jtag_unit_test(dut
, BS_EXTEST
, False, bsdata
, mask_outputs
)
668 yield from jtag_unit_test(dut
, BS_SAMPLE
, False, bsdata
, mask_low
)
670 #yield from jtag_unit_test(dut, BS_SAMPLE, False, bsdata, mask_low)
672 # Run through GPIO, UART, and I2C tests so that all signals are asserted
673 #yield from test_gpios(dut)
674 #yield from test_uart(dut)
675 #yield from test_i2c(dut)
677 #yield from jtag_unit_test(dut, BS_EXTEST, True, emptydata, mask_inputs)
678 #yield from jtag_unit_test(dut, BS_SAMPLE, True, emptydata, mask_high)
680 print("JTAG Boundary Scan Chain Test PASSED!")
683 def jtag_unit_test(dut
, bs_type
, is_io_set
, bsdata
, expected
):
684 bslen
= len(dut
.jtag
.ios
) #* 2
685 print("Chain len based on jtag.ios: {}".format(bslen
))
686 if bs_type
== BS_EXTEST
:
687 print("Sending TDI data with core/pads disconnected")
688 elif bs_type
== BS_SAMPLE
:
689 print("Sending TDI data with core/pads connected")
691 raise Exception("Unsupported BS chain mode!")
694 print("All pad inputs/core outputs set, bs data: {0:b}"
697 print("All pad inputs/core outputs reset, bs data: {0:b}"
700 result
= yield from jtag_read_write_reg(dut
.jtag
, bs_type
, bslen
, bsdata
)
702 # TODO: TDO data does not always match the signal states, maybe JTAG reset?
703 # TODO: make format based on bslen, not a magic number 20-bits wide
704 print("TDI BS Data: {0:020b}, Data Length (bits): {1}"
705 .format(bsdata
, bslen
))
706 print("TDO BS Data: {0:020b}".format(result
))
707 yield from check_ios_keys(dut
, expected
)
709 yield # testing extra clock
710 # Reset shift register between tests
711 yield from jtag_set_reset(dut
.jtag
)
714 def check_ios_keys(dut
, test_vector
):
715 print("Checking ios signals with given test vector")
716 bslen
= len(dut
.jtag
.ios
)
717 ios_keys
= list(dut
.jtag
.ios
.keys())
718 for i
in range(0, bslen
):
720 test_value
= (test_vector
>> i
) & 0b1
721 # Only observed signals so far are outputs...
722 if check_if_signal_output(ios_keys
[i
]):
723 temp_result
= yield dut
.jtag
.boundary_scan_pads
[signal
]['o']
724 print("Core Output | Name: ", signal
, " Value: ", temp_result
)
726 elif check_if_signal_input(ios_keys
[i
]):
727 temp_result
= yield dut
.jtag
.boundary_scan_pads
[signal
]['i']
728 print("Pad Input | Name: ", signal
, " Value: ", temp_result
)
730 raise Exception("Signal in JTAG ios dict: " + signal
731 + " cannot be determined as input or output!")
732 #assert temp_result == test_value
734 # TODO: may need to expand to support further signals contained in the
735 # JTAG module ios dictionary!
738 def check_if_signal_output(signal_str
):
739 if ('__o' in signal_str
) or ('__tx' in signal_str
):
745 def check_if_signal_input(signal_str
):
746 if ('__i' in signal_str
) or ('__rx' in signal_str
):
752 def produce_ios_io_mask(dut
, is_input
=False):
757 print("Determine the", mask_type
, "mask")
758 bslen
= len(dut
.jtag
.ios
)
759 ios_keys
= list(dut
.jtag
.ios
.keys())
761 for i
in range(0, bslen
):
763 if (('__o' in ios_keys
[i
]) or ('__tx' in ios_keys
[i
])):
764 if is_input
== False:
772 def print_all_ios_keys(dut
):
773 print("Print all ios keys")
774 bslen
= len(dut
.jtag
.ios
)
775 ios_keys
= list(dut
.jtag
.ios
.keys())
776 for i
in range(0, bslen
):
778 # Check if outputs are asserted
779 if ('__o' in ios_keys
[i
]) or ('__tx' in ios_keys
[i
]):
780 print("Core Output | Name: ", signal
)
782 print("Pad Input | Name: ", signal
)
785 # Copied from test_jtag_tap.py
786 # JTAG-ircodes for accessing DMI
791 # JTAG-ircodes for accessing Wishbone
797 def test_jtag_dmi_wb():
800 print("JTAG BS Reset")
801 yield from jtag_set_reset(top
.jtag
)
803 print("JTAG I/O dictionary of core/pad signals:")
804 print(top
.jtag
.ios
.keys())
806 # Copied from test_jtag_tap
807 # Don't know if the ID is the same for all JTAG instances
808 ####### JTAGy stuff (IDCODE) ######
811 idcode
= yield from jtag_read_write_reg(top
.jtag
, 0b1, 32)
812 print("idcode", hex(idcode
))
813 assert idcode
== 0x18ff
815 ####### JTAG to DMI ######
818 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, DBGCore
.CTRL
)
820 # read DMI CTRL register
821 status
= yield from jtag_read_write_reg(top
.jtag
, DMI_READ
, 64)
822 print("dmi ctrl status", hex(status
))
826 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, 0)
828 # write DMI CTRL register
829 status
= yield from jtag_read_write_reg(top
.jtag
, DMI_WRRD
, 64, 0b101)
830 print("dmi ctrl status", hex(status
))
831 # assert status == 4 # returned old value (nice! cool feature!)
834 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, DBGCore
.CTRL
)
836 # read DMI CTRL register
837 status
= yield from jtag_read_write_reg(top
.jtag
, DMI_READ
, 64)
838 print("dmi ctrl status", hex(status
))
841 # write DMI MSR address
842 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, DBGCore
.MSR
)
844 # read DMI MSR register
845 msr
= yield from jtag_read_write_reg(top
.jtag
, DMI_READ
, 64)
846 print("dmi msr", hex(msr
))
847 #assert msr == 0xdeadbeef
849 ####### JTAG to Wishbone ######
851 # write Wishbone address
852 yield from jtag_read_write_reg(top
.jtag
, WB_ADDR
, 16, 0x18)
854 # write/read wishbone data
855 data
= yield from jtag_read_write_reg(top
.jtag
, WB_WRRD
, 16, 0xfeef)
856 print("wb write", hex(data
))
858 # write Wishbone address
859 yield from jtag_read_write_reg(top
.jtag
, WB_ADDR
, 16, 0x18)
861 # write/read wishbone data
862 data
= yield from jtag_read_write_reg(top
.jtag
, WB_READ
, 16, 0)
863 print("wb read", hex(data
))
865 ####### done - tell dmi_sim to stop (otherwise it won't) ########
870 def test_debug_print(dut
):
871 print("Test used for getting object methods/information")
872 print("Moved here to clear clutter of gpio test")
874 print("printing out info about the resource gpio0")
875 print(dut
.gpio
['gpio0']['i'])
876 print("this is a PIN resource", type(dut
.gpio
['gpio0']['i']))
877 # yield can only be done on SIGNALS or RECORDS,
878 # NOT Pins/Resources gpio0_core_in = yield top.gpio['gpio0']['i']
879 #print("Test gpio0 core in: ", gpio0_core_in)
882 print(dut
.jtag
.__class
__.__name
__, dir(dut
.jtag
))
884 print(dut
.__class
__.__name
__, dir(dut
))
886 print(dut
.ports
.__class
__.__name
__, dir(dut
.ports
))
888 print(dut
.gpio
.__class
__.__name
__, dir(dut
.gpio
))
891 print(dir(dut
.jtag
.boundary_scan_pads
['uart_0__rx__pad__i']))
892 print(dut
.jtag
.boundary_scan_pads
['uart_0__rx__pad__i'].keys())
893 print(dut
.jtag
.boundary_scan_pads
['uart_0__tx__pad__o'])
894 # print(type(dut.jtag.boundary_scan_pads['uart_0__rx__pad__i']['rx']))
895 print("jtag pad table keys")
896 print(dut
.jtag
.resource_table_pads
.keys())
897 print(type(dut
.jtag
.resource_table_pads
[('uart', 0)].rx
.i
))
898 print(dut
.jtag
.boundary_scan_pads
['uart_0__rx__i'])
901 print(dut
.jtag
.boundary_scan_pads
['i2c_0__sda__i'])
902 print(type(dut
.jtag
.boundary_scan_pads
['i2c_0__sda__i']['i']))
904 print(dut
.jtag
.resource_table_pads
)
905 print(dut
.jtag
.boundary_scan_pads
)
907 # Trying to read input from core side, looks like might be a pin...
908 # XXX don't "look like" - don't guess - *print it out*
909 #print ("don't guess, CHECK", type(top.gpio.gpio0.i))
911 print() # extra print to divide the output
915 def setup_blinker(build_blinker
=False):
917 and to create a Platform instance with that list, and build
921 p.resources=listofstuff
925 pinset
= dummy_pinset()
927 resources
= create_resources(pinset
)
928 top
= Blinker(pinset
, resources
, no_jtag_connect
=False) # True)
930 vl
= rtlil
.convert(top
, ports
=top
.ports())
931 with
open("test_jtag_blinker.il", "w") as f
:
935 # XXX these modules are all being added *AFTER* the build process links
936 # everything together. the expectation that this would work is...
937 # unrealistic. ordering, clearly, is important.
939 # This JTAG code copied from test, probably not needed
940 # dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
941 top
.jtag
.stop
= False
942 # rather than the client access the JTAG bus directly
943 # create an alternative that the client sets
948 cdut
.cbus
= JTAGInterface()
950 # set up client-server on port 44843-something
951 top
.jtag
.s
= JTAGServer()
952 cdut
.c
= JTAGClient()
953 top
.jtag
.s
.get_connection()
955 # print ("running server only as requested,
956 # use openocd remote to test")
958 # top.jtag.s.get_connection(None) # block waiting for connection
960 # take copy of ir_width and scan_len
961 cdut
._ir
_width
= top
.jtag
._ir
_width
962 cdut
.scan_len
= top
.jtag
.scan_len
964 p
= ASICPlatform(resources
, top
.jtag
)
966 # this is what needs to gets treated as "top", after "main module" top
967 # is augmented with IO pads with JTAG tacked on. the expectation that
968 # the get_input() etc functions will be called magically by some other
969 # function is unrealistic.
970 top_fragment
= p
.fragment
976 dut
= setup_blinker(build_blinker
=False)
978 # XXX simulating top (the module that does not itself contain IO pads
979 # because that's covered by build) cannot possibly be expected to work
980 # particularly when modules have been added *after* the platform build()
981 # function has been called.
984 sim
.add_clock(1e-6, domain
="sync") # standard clock
986 # sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
987 # if len(sys.argv) != 2 or sys.argv[1] != 'server':
989 #sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag)))
990 # handles (pretends to be) DMI
991 # sim.add_sync_process(wrap(dmi_sim(top.jtag)))
993 # sim.add_sync_process(wrap(test_gpios(top)))
994 # sim.add_sync_process(wrap(test_uart(top)))
995 # sim.add_sync_process(wrap(test_i2c(top)))
996 # sim.add_sync_process(wrap(test_debug_print()))
998 sim
.add_sync_process(wrap(test_jtag_bs_chain(dut
)))
1000 with sim
.write_vcd("blinker_test.vcd"):
1004 if __name__
== '__main__':