f81311a2b803dbdbc73ee14c83837b33e532e0a1
3 pinmux documented here https://libre-soc.org/docs/pinmux/
5 from nmigen
.build
.dsl
import Resource
, Subsignal
, Pins
6 from nmigen
.build
.plat
import TemplatedPlatform
7 from nmigen
.build
.res
import ResourceManager
, ResourceError
8 from nmigen
.hdl
.rec
import Layout
9 from nmigen
import Elaboratable
, Signal
, Module
, Instance
10 from collections
import OrderedDict
11 from jtag
import JTAG
, resiotypes
12 from copy
import deepcopy
13 from nmigen
.cli
import rtlil
16 # extra dependencies for jtag testing (?)
17 #from soc.bus.sram import SRAM
19 #from nmigen import Memory
20 from nmigen
.sim
import Simulator
, Delay
, Settle
, Tick
, Passive
22 from nmutil
.util
import wrap
24 #from soc.debug.jtagutils import (jtag_read_write_reg,
25 # jtag_srv, jtag_set_reset,
26 # jtag_set_ir, jtag_set_get_dr)
28 from soc
.debug
.test
.test_jtag_tap
import (jtag_read_write_reg
,
35 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
36 from c4m
.nmigen
.jtag
.bus
import Interface
as JTAGInterface
37 from soc
.debug
.dmi
import DMIInterface
, DBGCore
38 #from soc.debug.test.dmi_sim import dmi_sim
39 #from soc.debug.test.jtagremote import JTAGServer, JTAGClient
40 from nmigen
.build
.res
import ResourceError
42 # Was thinking of using these functions, but skipped for simplicity for now
43 # XXX nope. the output from JSON file.
44 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
45 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
46 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
48 # File for stage 1 pinmux tested proposed by Luke,
49 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
53 # sigh this needs to come from pinmux.
56 gpios
.append("%d*" % i
)
57 return {'uart': ['tx+', 'rx-'],
59 #'jtag': ['tms-', 'tdi-', 'tdo+', 'tck+'],
60 'i2c': ['sda*', 'scl+']}
63 a function is needed which turns the results of dummy_pinset()
66 [UARTResource("uart", 0, tx=..., rx=..),
67 I2CResource("i2c", 0, scl=..., sda=...),
68 Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
69 Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
75 def create_resources(pinset
):
77 for periph
, pins
in pinset
.items():
80 #print("I2C required!")
81 resources
.append(I2CResource('i2c', 0, sda
='sda', scl
='scl'))
82 elif periph
== 'uart':
83 #print("UART required!")
84 resources
.append(UARTResource('uart', 0, tx
='tx', rx
='rx'))
85 elif periph
== 'gpio':
86 #print("GPIO required!")
87 print ("GPIO is defined as '*' type, meaning i, o and oe needed")
90 pname
= "gpio"+pin
[:-1] # strip "*" on end
91 # urrrr... tristsate and io assume a single pin which is
92 # of course exactly what we don't want in an ASIC: we want
93 # *all three* pins but the damn port is not outputted
94 # as a triplet, it's a single Record named "io". sigh.
95 # therefore the only way to get a triplet of i/o/oe
96 # is to *actually* create explicit triple pins
97 # XXX ARRRGH, doesn't work
98 #pad = Subsignal("io",
99 # Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
100 # dir="io", assert_width=3))
101 #ios.append(Resource(pname, 0, pad))
103 pads
.append(Subsignal("i",
104 Pins(pname
+"_i", dir="i", assert_width
=1)))
105 pads
.append(Subsignal("o",
106 Pins(pname
+"_o", dir="o", assert_width
=1)))
107 pads
.append(Subsignal("oe",
108 Pins(pname
+"_oe", dir="o", assert_width
=1)))
109 ios
.append(Resource
.family(pname
, 0, default_name
=pname
,
111 resources
.append(Resource
.family(periph
, 0, default_name
="gpio",
114 # add clock and reset
115 clk
= Resource("clk", 0, Pins("sys_clk", dir="i"))
116 rst
= Resource("rst", 0, Pins("sys_rst", dir="i"))
117 resources
.append(clk
)
118 resources
.append(rst
)
122 def JTAGResource(*args
):
124 io
.append(Subsignal("tms", Pins("tms", dir="i", assert_width
=1)))
125 io
.append(Subsignal("tdi", Pins("tdi", dir="i", assert_width
=1)))
126 io
.append(Subsignal("tck", Pins("tck", dir="i", assert_width
=1)))
127 io
.append(Subsignal("tdo", Pins("tdo", dir="o", assert_width
=1)))
128 return Resource
.family(*args
, default_name
="jtag", ios
=io
)
130 def UARTResource(*args
, rx
, tx
):
132 io
.append(Subsignal("rx", Pins(rx
, dir="i", assert_width
=1)))
133 io
.append(Subsignal("tx", Pins(tx
, dir="o", assert_width
=1)))
134 return Resource
.family(*args
, default_name
="uart", ios
=io
)
137 def I2CResource(*args
, scl
, sda
):
140 pads
.append(Subsignal("i", Pins(sda
+"_i", dir="i", assert_width
=1)))
141 pads
.append(Subsignal("o", Pins(sda
+"_o", dir="o", assert_width
=1)))
142 pads
.append(Subsignal("oe", Pins(sda
+"_oe", dir="o", assert_width
=1)))
143 ios
.append(Resource
.family(sda
, 0, default_name
=sda
, ios
=pads
))
145 pads
.append(Subsignal("i", Pins(scl
+"_i", dir="i", assert_width
=1)))
146 pads
.append(Subsignal("o", Pins(scl
+"_o", dir="o", assert_width
=1)))
147 pads
.append(Subsignal("oe", Pins(scl
+"_oe", dir="o", assert_width
=1)))
148 ios
.append(Resource
.family(scl
, 0, default_name
=scl
, ios
=pads
))
149 return Resource
.family(*args
, default_name
="i2c", ios
=ios
)
152 # top-level demo module.
153 class Blinker(Elaboratable
):
154 def __init__(self
, pinset
, resources
, no_jtag_connect
=False):
155 self
.no_jtag_connect
= no_jtag_connect
156 self
.jtag
= JTAG({}, "sync", resources
=resources
)
157 #memory = Memory(width=32, depth=16)
158 #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
160 def elaborate(self
, platform
):
161 jtag_resources
= self
.jtag
.pad_mgr
.resources
163 m
.submodules
.jtag
= self
.jtag
164 #m.submodules.sram = self.sram
167 #m.d.sync += count.eq(count+1)
168 print ("resources", platform
, jtag_resources
.items())
169 gpio
= self
.jtag
.request('gpio')
170 print (gpio
, gpio
.layout
, gpio
.fields
)
171 # get the GPIO bank, mess about with some of the pins
172 #m.d.comb += gpio.gpio0.o.eq(1)
173 #m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
174 #m.d.comb += gpio.gpio1.oe.eq(count[4])
175 #m.d.sync += count[0].eq(gpio.gpio1.i)
178 gpio_i_ro
= Signal(num_gpios
)
179 gpio_o_test
= Signal(num_gpios
)
180 gpio_oe_test
= Signal(num_gpios
)
182 # Create a read-only copy of core-side GPIO input signals
183 # for Simulation asserts
184 m
.d
.comb
+= gpio_i_ro
[0].eq(gpio
.gpio0
.i
)
185 m
.d
.comb
+= gpio_i_ro
[1].eq(gpio
.gpio1
.i
)
186 m
.d
.comb
+= gpio_i_ro
[2].eq(gpio
.gpio2
.i
)
187 m
.d
.comb
+= gpio_i_ro
[3].eq(gpio
.gpio3
.i
)
189 # Wire up the output signal of each gpio by XOR'ing each bit of
190 # gpio_o_test with gpio's input
191 # Wire up each bit of gpio_oe_test signal to oe signal of each gpio.
192 # Turn into a loop at some point, probably a way without
194 m
.d
.comb
+= gpio
.gpio0
.o
.eq(gpio_o_test
[0] ^ gpio
.gpio0
.i
)
195 m
.d
.comb
+= gpio
.gpio1
.o
.eq(gpio_o_test
[1] ^ gpio
.gpio1
.i
)
196 m
.d
.comb
+= gpio
.gpio2
.o
.eq(gpio_o_test
[2] ^ gpio
.gpio2
.i
)
197 m
.d
.comb
+= gpio
.gpio3
.o
.eq(gpio_o_test
[3] ^ gpio
.gpio3
.i
)
199 m
.d
.comb
+= gpio
.gpio0
.oe
.eq(gpio_oe_test
[0])
200 m
.d
.comb
+= gpio
.gpio1
.oe
.eq(gpio_oe_test
[1])
201 m
.d
.comb
+= gpio
.gpio2
.oe
.eq(gpio_oe_test
[2])
202 m
.d
.comb
+= gpio
.gpio3
.oe
.eq(gpio_oe_test
[3])
204 # get the UART resource, mess with the output tx
205 uart
= self
.jtag
.request('uart')
206 print ("uart fields", uart
, uart
.fields
)
207 self
.intermediary
= Signal()
208 m
.d
.comb
+= uart
.tx
.eq(self
.intermediary
)
209 m
.d
.comb
+= self
.intermediary
.eq(uart
.rx
)
213 i2c_sda_oe_test
= Signal(num_i2c
)
214 i2c_scl_oe_test
= Signal(num_i2c
)
215 i2c
= self
.jtag
.request('i2c')
216 print ("i2c fields", i2c
, i2c
.fields
)
217 # Connect in loopback
218 m
.d
.comb
+= i2c
.scl
.o
.eq(i2c
.scl
.i
)
219 m
.d
.comb
+= i2c
.sda
.o
.eq(i2c
.sda
.i
)
220 # Connect output enable to test port for sim
221 m
.d
.comb
+= i2c
.sda
.oe
.eq(i2c_sda_oe_test
)
222 m
.d
.comb
+= i2c
.scl
.oe
.eq(i2c_scl_oe_test
)
224 # to even be able to get at objects, you first have to make them
225 # available - i.e. not as local variables
226 # Public attributes are equivalent to input/output ports in hdl's
230 self
.i2c_sda_oe_test
= i2c_sda_oe_test
231 self
.i2c_scl_oe_test
= i2c_scl_oe_test
232 self
.gpio_i_ro
= gpio_i_ro
233 self
.gpio_o_test
= gpio_o_test
234 self
.gpio_oe_test
= gpio_oe_test
236 # sigh these wire up to the pads so you cannot set Signals
237 # that are already wired
238 if self
.no_jtag_connect
: # bypass jtag pad connect for testing purposes
240 return self
.jtag
.boundary_elaborate(m
, platform
)
246 yield from self
.jtag
.iter_ports()
249 _trellis_command_templates = [
251 {{invoke_tool("yosys")}}
253 {{get_override("yosys_opts")|options}}
260 # sigh, have to create a dummy platform for now.
261 # TODO: investigate how the heck to get it to output ilang. or verilog.
262 # or, anything, really. but at least it doesn't barf
263 class ASICPlatform(TemplatedPlatform
):
265 resources
= OrderedDict()
267 command_templates
= ['/bin/true'] # no command needed: stops barfing
269 **TemplatedPlatform
.build_script_templates
,
274 "{{name}}.debug.v": r
"""
275 /* {{autogenerated}} */
276 {{emit_debug_verilog()}}
280 default_clk
= "clk" # should be picked up / overridden by platform sys.clk
281 default_rst
= "rst" # should be picked up / overridden by platform sys.rst
283 def __init__(self
, resources
, jtag
):
287 # create set of pin resources based on the pinset, this is for the core
288 #jtag_resources = self.jtag.pad_mgr.resources
289 self
.add_resources(resources
)
291 # add JTAG without scan
292 self
.add_resources([JTAGResource('jtag', 0)], no_boundary_scan
=True)
294 def add_resources(self
, resources
, no_boundary_scan
=False):
295 print ("ASICPlatform add_resources", resources
)
296 return super().add_resources(resources
)
298 #def iter_ports(self):
299 # yield from super().iter_ports()
300 # for io in self.jtag.ios.values():
301 # print ("iter ports", io.layout, io)
302 # for field in io.core.fields:
303 # yield getattr(io.core, field)
304 # for field in io.pad.fields:
305 # yield getattr(io.pad, field)
307 # XXX these aren't strictly necessary right now but the next
308 # phase is to add JTAG Boundary Scan so it maaay be worth adding?
309 # at least for the print statements
310 def get_input(self
, pin
, port
, attrs
, invert
):
311 self
._check
_feature
("single-ended input", pin
, attrs
,
312 valid_xdrs
=(0,), valid_attrs
=None)
315 print (" get_input", pin
, "port", port
, port
.layout
)
316 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
319 def get_output(self
, pin
, port
, attrs
, invert
):
320 self
._check
_feature
("single-ended output", pin
, attrs
,
321 valid_xdrs
=(0,), valid_attrs
=None)
324 print (" get_output", pin
, "port", port
, port
.layout
)
325 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, pin
.o
))
328 def get_tristate(self
, pin
, port
, attrs
, invert
):
329 self
._check
_feature
("single-ended tristate", pin
, attrs
,
330 valid_xdrs
=(0,), valid_attrs
=None)
332 print (" get_tristate", pin
, "port", port
, port
.layout
)
334 print (" pad", pin
, port
, attrs
)
335 print (" pin", pin
.layout
)
337 # m.submodules += Instance("$tribuf",
340 # i_A=self._invert_if(invert, pin.o),
343 m
.d
.comb
+= io
.core
.o
.eq(pin
.o
)
344 m
.d
.comb
+= io
.core
.oe
.eq(pin
.oe
)
345 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
346 m
.d
.comb
+= io
.pad
.i
.eq(port
.i
)
347 m
.d
.comb
+= port
.o
.eq(io
.pad
.o
)
348 m
.d
.comb
+= port
.oe
.eq(io
.pad
.oe
)
351 def get_input_output(self
, pin
, port
, attrs
, invert
):
352 self
._check
_feature
("single-ended input/output", pin
, attrs
,
353 valid_xdrs
=(0,), valid_attrs
=None)
355 print (" get_input_output", pin
, "port", port
, port
.layout
)
357 print (" port layout", port
.layout
)
359 print (" layout", pin
.layout
)
360 #m.submodules += Instance("$tribuf",
363 # i_A=self._invert_if(invert, io.pad.o),
366 # Create aliases for the port sub-signals
371 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port_i
))
372 m
.d
.comb
+= port_o
.eq(self
._invert
_if
(invert
, pin
.o
))
373 m
.d
.comb
+= port_oe
.eq(pin
.oe
)
377 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
378 """override toolchain_prepare in order to grab the fragment
380 self
.fragment
= fragment
381 return super().toolchain_prepare(fragment
, name
, **kwargs
)
386 print("Starting sanity test case!")
387 print("printing out list of stuff in top")
388 print ("JTAG IOs", top
.jtag
.ios
)
389 # ok top now has a variable named "gpio", let's enumerate that too
390 print("printing out list of stuff in top.gpio and its type")
391 print(top
.gpio
.__class
__.__name
__, dir(top
.gpio
))
392 # ok, it's a nmigen Record, therefore it has a layout. let's print
394 print("top.gpio is a Record therefore has fields and a layout")
395 print(" layout:", top
.gpio
.layout
)
396 print(" fields:", top
.gpio
.fields
)
397 print("Fun never ends...")
398 print(" layout, gpio2:", top
.gpio
.layout
['gpio2'])
399 print(" fields, gpio2:", top
.gpio
.fields
['gpio2'])
400 print(top
.jtag
.__class
__.__name
__, dir(top
.jtag
))
402 print(top
.jtag
.resource_table_pads
[('gpio', 0)])
404 # etc etc. you get the general idea
406 yield top
.uart
.rx
.eq(0)
407 yield Delay(delayVal
)
409 yield top
.gpio
.gpio2
.o
.eq(0)
410 yield top
.gpio
.gpio3
.o
.eq(1)
412 yield top
.gpio
.gpio3
.oe
.eq(1)
414 yield top
.gpio
.gpio3
.oe
.eq(0)
415 # grab the JTAG resource pad
416 gpios_pad
= top
.jtag
.resource_table_pads
[('gpio', 0)]
417 yield gpios_pad
.gpio3
.i
.eq(1)
418 yield Delay(delayVal
)
420 yield top
.gpio
.gpio2
.oe
.eq(1)
421 yield top
.gpio
.gpio3
.oe
.eq(1)
422 yield gpios_pad
.gpio3
.i
.eq(0)
423 yield top
.jtag
.gpio
.gpio2
.i
.eq(1)
424 yield Delay(delayVal
)
428 # get a value first (as an integer). you were trying to set
429 # it to the actual Signal. this is not going to work. or if
430 # it does, it's very scary.
431 gpio_o2
= not gpio_o2
432 yield top
.gpio
.gpio2
.o
.eq(gpio_o2
)
434 # ditto: here you are trying to set to an AST expression
435 # which is inadviseable (likely to fail)
436 gpio_o3
= not gpio_o2
437 yield top
.gpio
.gpio3
.o
.eq(gpio_o3
)
438 yield Delay(delayVal
)
440 # grab the JTAG resource pad
441 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
442 yield uart_pad
.rx
.i
.eq(gpio_o2
)
443 yield Delay(delayVal
)
445 yield # one clock cycle
446 tx_val
= yield uart_pad
.tx
.o
447 print ("xmit uart", tx_val
, gpio_o2
)
449 print ("jtag pad table keys")
450 print (top
.jtag
.resource_table_pads
.keys())
451 uart_pad
= top
.jtag
.resource_table_pads
[('uart', 0)]
452 print ("uart pad", uart_pad
)
453 print ("uart pad", uart_pad
.layout
)
455 yield top
.gpio
.gpio2
.oe
.eq(0)
456 yield top
.gpio
.gpio3
.oe
.eq(0)
457 yield top
.jtag
.gpio
.gpio2
.i
.eq(0)
458 yield Delay(delayVal
)
462 print("Starting GPIO test case!")
463 # TODO: make pad access parametrisable to cope with more than 4 GPIOs
464 num_gpios
= dut
.gpio_o_test
.width
465 # Grab GPIO outpud pad resource from JTAG BS - end of chain
466 print (dut
.jtag
.boundary_scan_pads
.keys())
467 gpio0_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio0__o']['o']
468 gpio1_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio1__o']['o']
469 gpio2_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio2__o']['o']
470 gpio3_o
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio3__o']['o']
471 gpio_pad_out
= [ gpio0_o
, gpio1_o
, gpio2_o
, gpio3_o
]
473 # Grab GPIO output enable pad resource from JTAG BS - end of chain
474 gpio0_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio0__oe']['o']
475 gpio1_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio1__oe']['o']
476 gpio2_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio2__oe']['o']
477 gpio3_oe
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio3__oe']['o']
478 gpio_pad_oe
= [gpio0_oe
, gpio1_oe
, gpio2_oe
, gpio3_oe
]
480 # Grab GPIO input pad resource from JTAG BS - start of chain
481 gpio0_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio0__i']['i']
482 gpio1_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio1__i']['i']
483 gpio2_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio2__i']['i']
484 gpio3_pad_in
= dut
.jtag
.boundary_scan_pads
['gpio_0__gpio3__i']['i']
485 gpio_pad_in
= [gpio0_pad_in
, gpio1_pad_in
, gpio2_pad_in
, gpio3_pad_in
]
487 # Have the sim run through a for-loop where the gpio_o_test is
488 # incremented like a counter (0000, 0001...)
489 # At each iteration of the for-loop, assert:
490 # + output set at core matches output seen at pad
491 # TODO + input set at pad matches input seen at core
492 # TODO + if gpio_o_test bit is cleared, output seen at pad matches
494 num_gpio_o_states
= num_gpios
**2
495 pad_out
= [0] * num_gpios
496 pad_oe
= [0] * num_gpios
497 #print("Num of permutations of gpio_o_test record: ", num_gpio_o_states)
498 for gpio_o_val
in range(0, num_gpio_o_states
):
499 yield dut
.gpio_o_test
.eq(gpio_o_val
)
501 yield # Move to the next clk cycle
503 # Cycle through all input combinations
504 for gpio_i_val
in range(0, num_gpio_o_states
):
505 # Set each gpio input at pad to test value
506 for gpio_bit
in range(0, num_gpios
):
507 yield gpio_pad_in
[gpio_bit
].eq((gpio_i_val
>> gpio_bit
) & 0x1)
509 # After changing the gpio0/1/2/3 inputs,
510 # the output is also going to change.
511 # *therefore it must be read again* to get the
512 # snapshot (as a python value)
513 for gpio_bit
in range(0, num_gpios
):
514 pad_out
[gpio_bit
] = yield gpio_pad_out
[gpio_bit
]
516 for gpio_bit
in range(0, num_gpios
):
517 # check core and pad in
518 gpio_i_ro
= yield dut
.gpio_i_ro
[gpio_bit
]
519 out_test_bit
= ((gpio_o_val
& (1 << gpio_bit
)) != 0)
520 in_bit
= ((gpio_i_val
& (1 << gpio_bit
)) != 0)
521 # Check that the core end input matches pad
522 assert in_bit
== gpio_i_ro
523 # Test that the output at pad matches:
524 # Pad output == given test output XOR test input
525 assert (out_test_bit ^ in_bit
) == pad_out
[gpio_bit
]
527 # For debugging - VERY verbose
528 #print("---------------------")
529 #print("Test Out: ", bin(gpio_o_val))
530 #print("Test Input: ", bin(gpio_i_val))
532 #print("Pad Output: ", list(reversed(pad_out)))
533 #print("---------------------")
535 # For-loop for testing output enable signals
536 for gpio_o_val
in range(0, num_gpio_o_states
):
537 yield dut
.gpio_oe_test
.eq(gpio_o_val
)
538 yield # Move to the next clk cycle
540 for gpio_bit
in range(0, num_gpios
):
541 pad_oe
[gpio_bit
] = yield gpio_pad_oe
[gpio_bit
]
544 for gpio_bit
in range(0, num_gpios
):
545 oe_test_bit
= ((gpio_o_val
& (1 << gpio_bit
)) != 0)
546 # oe set at core matches oe seen at pad:
547 assert oe_test_bit
== pad_oe
[gpio_bit
]
548 # For debugging - VERY verbose
549 #print("---------------------")
550 #print("Test Output Enable: ", bin(gpio_o_val))
552 #print("Pad Output Enable: ", list(reversed(pad_oe)))
553 #print("---------------------")
555 # Reset test ouput register
556 yield dut
.gpio_o_test
.eq(0)
557 print("GPIO Test PASSED!")
560 # grab the JTAG resource pad
562 print ("bs pad keys", dut
.jtag
.boundary_scan_pads
.keys())
564 uart_rx_pad
= dut
.jtag
.boundary_scan_pads
['uart_0__rx']['i']
565 uart_tx_pad
= dut
.jtag
.boundary_scan_pads
['uart_0__tx']['o']
567 print ("uart rx pad", uart_rx_pad
)
568 print ("uart tx pad", uart_tx_pad
)
570 # Test UART by writing 0 and 1 to RX
571 # Internally TX connected to RX,
572 # so match pad TX with RX
573 for i
in range(0, 2):
574 yield uart_rx_pad
.eq(i
)
575 #yield uart_rx_pad.eq(i)
577 yield # one clock cycle
578 tx_val
= yield uart_tx_pad
579 print ("xmit uart", tx_val
, 1)
582 print("UART Test PASSED!")
585 i2c_sda_i_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__sda__i']['i']
586 i2c_sda_o_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__sda__o']['o']
587 i2c_sda_oe_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__sda__oe']['o']
589 i2c_scl_i_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__scl__i']['i']
590 i2c_scl_o_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__scl__o']['o']
591 i2c_scl_oe_pad
= dut
.jtag
.boundary_scan_pads
['i2c_0__scl__oe']['o']
593 #i2c_pad = dut.jtag.resource_table_pads[('i2c', 0)]
594 #print ("i2c pad", i2c_pad)
595 #print ("i2c pad", i2c_pad.layout)
597 for i
in range(0, 2):
598 yield i2c_sda_i_pad
.eq(i
) #i2c_pad.sda.i.eq(i)
599 yield i2c_scl_i_pad
.eq(i
) #i2c_pad.scl.i.eq(i)
600 yield dut
.i2c_sda_oe_test
.eq(i
)
601 yield dut
.i2c_scl_oe_test
.eq(i
)
603 yield # one clock cycle
604 sda_o_val
= yield i2c_sda_o_pad
605 scl_o_val
= yield i2c_scl_o_pad
606 sda_oe_val
= yield i2c_sda_oe_pad
607 scl_oe_val
= yield i2c_scl_oe_pad
608 print ("Test input: ", i
, " SDA/SCL out: ", sda_o_val
, scl_o_val
,
609 " SDA/SCL oe: ", sda_oe_val
, scl_oe_val
)
610 assert sda_o_val
== i
611 assert scl_o_val
== i
612 assert sda_oe_val
== i
613 assert scl_oe_val
== i
615 print("I2C Test PASSED!")
617 # JTAG boundary scan reg addresses - See c4m/nmigen/jtag/tap.py line #357
622 def test_jtag_bs_chain(dut
):
623 #print(dir(dut.jtag))
626 print("JTAG BS Reset")
627 yield from jtag_set_reset(dut
.jtag
)
629 #print("JTAG I/O dictionary of core/pad signals:")
630 #print(dut.jtag.ios.keys())
632 # Based on number of ios entries, produce a test shift reg pattern
633 bslen
= len(dut
.jtag
.ios
)
634 bsdata
= 2**bslen
- 1 # Fill with all 1s for now
635 fulldata
= bsdata
# for testing
636 emptydata
= 0 # for testing
638 mask_inputs
= produce_ios_io_mask(dut
, is_input
=True)
639 mask_outputs
= produce_ios_io_mask(dut
, is_input
=False)
643 # TODO: make format based on bslen, not a magic number 20-bits wide
644 print("Input Mask: {0:20b}".format(mask_inputs
))
645 print("Output Mask: {0:20b}".format(mask_outputs
))
647 yield from jtag_unit_test(dut
, BS_EXTEST
, False, bsdata
, mask_outputs
)
648 yield from jtag_unit_test(dut
, BS_SAMPLE
, False, bsdata
, mask_low
)
650 # Run through GPIO, UART, and I2C tests so that all signals are asserted
651 yield from test_gpios(dut
)
652 yield from test_uart(dut
)
653 yield from test_i2c(dut
)
655 yield from jtag_unit_test(dut
, BS_EXTEST
, True, emptydata
, mask_inputs
)
656 yield from jtag_unit_test(dut
, BS_SAMPLE
, True, emptydata
, mask_high
)
658 print("JTAG Boundary Scan Chain Test PASSED!")
660 def jtag_unit_test(dut
, bs_type
, is_io_set
, bsdata
, expected
):
661 bslen
= len(dut
.jtag
.ios
)
662 if bs_type
== BS_EXTEST
:
663 print("Sending TDI data with core/pads disconnected")
664 elif bs_type
== BS_SAMPLE
:
665 print("Sending TDI data with core/pads connected")
667 raise Exception("Unsupported BS chain mode!")
670 print("All pad inputs/core outputs set, bs data: {0:b}"
673 print("All pad inputs/core outputs reset, bs data: {0:b}"
676 result
= yield from jtag_read_write_reg(dut
.jtag
, bs_type
, bslen
, bsdata
)
678 # TODO: TDO data does not always match the signal states, maybe JTAG reset?
679 print("TDI BS Data: {0:b}, Data Length (bits): {1}".format(bsdata
, bslen
))
680 print("TDO BS Data: {0:b}".format(result
))
681 yield from check_ios_keys(dut
, expected
)
683 # Reset shift register between tests
684 yield from jtag_set_reset(dut
.jtag
)
686 def check_ios_keys(dut
, test_vector
):
687 print("Checking ios signals with given test vector")
688 bslen
= len(dut
.jtag
.ios
)
689 ios_keys
= list(dut
.jtag
.ios
.keys())
690 for i
in range(0, bslen
):
692 test_value
= (test_vector
>> i
) & 0b1
693 # Only observed signals so far are outputs...
694 if check_if_signal_output(ios_keys
[i
]):
695 temp_result
= yield dut
.jtag
.boundary_scan_pads
[signal
]['o']
696 print("Core Output | Name: ", signal
, " Value: ", temp_result
)
698 elif check_if_signal_input(ios_keys
[i
]):
699 temp_result
= yield dut
.jtag
.boundary_scan_pads
[signal
]['i']
700 print("Pad Input | Name: ", signal
, " Value: ", temp_result
)
702 raise Exception("Signal in JTAG ios dict: " + signal
703 + " cannot be determined as input or output!")
704 assert temp_result
== test_value
706 # TODO: may need to expand to support further signals contained in the
707 # JTAG module ios dictionary!
708 def check_if_signal_output(signal_str
):
709 if ('__o' in signal_str
) or ('__tx' in signal_str
):
714 def check_if_signal_input(signal_str
):
715 if ('__i' in signal_str
) or ('__rx' in signal_str
):
720 def produce_ios_io_mask(dut
, is_input
=False):
725 print("Determine the", mask_type
, "mask")
726 bslen
= len(dut
.jtag
.ios
)
727 ios_keys
= list(dut
.jtag
.ios
.keys())
729 for i
in range(0, bslen
):
731 if (('__o' in ios_keys
[i
]) or ('__tx' in ios_keys
[i
])):
732 if is_input
== False:
739 def print_all_ios_keys(dut
):
740 print("Print all ios keys")
741 bslen
= len(dut
.jtag
.ios
)
742 ios_keys
= list(dut
.jtag
.ios
.keys())
743 for i
in range(0, bslen
):
745 # Check if outputs are asserted
746 if ('__o' in ios_keys
[i
]) or ('__tx' in ios_keys
[i
]):
747 print("Core Output | Name: ", signal
)
749 print("Pad Input | Name: ", signal
)
753 # Copied from test_jtag_tap.py
754 # JTAG-ircodes for accessing DMI
759 # JTAG-ircodes for accessing Wishbone
764 def test_jtag_dmi_wb():
767 print("JTAG BS Reset")
768 yield from jtag_set_reset(top
.jtag
)
770 print("JTAG I/O dictionary of core/pad signals:")
771 print(top
.jtag
.ios
.keys())
773 # Copied from test_jtag_tap
774 # Don't know if the ID is the same for all JTAG instances
775 ####### JTAGy stuff (IDCODE) ######
778 idcode
= yield from jtag_read_write_reg(top
.jtag
, 0b1, 32)
779 print ("idcode", hex(idcode
))
780 assert idcode
== 0x18ff
782 ####### JTAG to DMI ######
785 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, DBGCore
.CTRL
)
787 # read DMI CTRL register
788 status
= yield from jtag_read_write_reg(top
.jtag
, DMI_READ
, 64)
789 print ("dmi ctrl status", hex(status
))
793 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, 0)
795 # write DMI CTRL register
796 status
= yield from jtag_read_write_reg(top
.jtag
, DMI_WRRD
, 64, 0b101)
797 print ("dmi ctrl status", hex(status
))
798 #assert status == 4 # returned old value (nice! cool feature!)
801 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, DBGCore
.CTRL
)
803 # read DMI CTRL register
804 status
= yield from jtag_read_write_reg(top
.jtag
, DMI_READ
, 64)
805 print ("dmi ctrl status", hex(status
))
808 # write DMI MSR address
809 yield from jtag_read_write_reg(top
.jtag
, DMI_ADDR
, 8, DBGCore
.MSR
)
811 # read DMI MSR register
812 msr
= yield from jtag_read_write_reg(top
.jtag
, DMI_READ
, 64)
813 print ("dmi msr", hex(msr
))
814 #assert msr == 0xdeadbeef
816 ####### JTAG to Wishbone ######
818 # write Wishbone address
819 yield from jtag_read_write_reg(top
.jtag
, WB_ADDR
, 16, 0x18)
821 # write/read wishbone data
822 data
= yield from jtag_read_write_reg(top
.jtag
, WB_WRRD
, 16, 0xfeef)
823 print ("wb write", hex(data
))
825 # write Wishbone address
826 yield from jtag_read_write_reg(top
.jtag
, WB_ADDR
, 16, 0x18)
828 # write/read wishbone data
829 data
= yield from jtag_read_write_reg(top
.jtag
, WB_READ
, 16, 0)
830 print ("wb read", hex(data
))
832 ####### done - tell dmi_sim to stop (otherwise it won't) ########
836 def test_debug_print(dut
):
837 print("Test used for getting object methods/information")
838 print("Moved here to clear clutter of gpio test")
840 print ("printing out info about the resource gpio0")
841 print (dut
.gpio
['gpio0']['i'])
842 print ("this is a PIN resource", type(dut
.gpio
['gpio0']['i']))
843 # yield can only be done on SIGNALS or RECORDS,
844 # NOT Pins/Resources gpio0_core_in = yield top.gpio['gpio0']['i']
845 #print("Test gpio0 core in: ", gpio0_core_in)
848 print(dut
.jtag
.__class
__.__name
__, dir(dut
.jtag
))
850 print(dut
.__class
__.__name
__, dir(dut
))
852 print(dut
.ports
.__class
__.__name
__, dir(dut
.ports
))
854 print(dut
.gpio
.__class
__.__name
__, dir(dut
.gpio
))
857 print(dir(dut
.jtag
.boundary_scan_pads
['uart_0__rx__pad__i']))
858 print(dut
.jtag
.boundary_scan_pads
['uart_0__rx__pad__i'].keys())
859 print(dut
.jtag
.boundary_scan_pads
['uart_0__tx__pad__o'])
860 #print(type(dut.jtag.boundary_scan_pads['uart_0__rx__pad__i']['rx']))
861 print ("jtag pad table keys")
862 print (dut
.jtag
.resource_table_pads
.keys())
863 print(type(dut
.jtag
.resource_table_pads
[('uart', 0)].rx
.i
))
864 print(dut
.jtag
.boundary_scan_pads
['uart_0__rx__i'])
867 print(dut
.jtag
.boundary_scan_pads
['i2c_0__sda__i'])
868 print(type(dut
.jtag
.boundary_scan_pads
['i2c_0__sda__i']['i']))
870 print(dut
.jtag
.resource_table_pads
)
871 print(dut
.jtag
.boundary_scan_pads
)
874 # Trying to read input from core side, looks like might be a pin...
875 # XXX don't "look like" - don't guess - *print it out*
876 #print ("don't guess, CHECK", type(top.gpio.gpio0.i))
878 print () # extra print to divide the output
881 def setup_blinker(build_blinker
=False):
883 and to create a Platform instance with that list, and build
887 p.resources=listofstuff
891 pinset
= dummy_pinset()
893 resources
= create_resources(pinset
)
894 top
= Blinker(pinset
, resources
, no_jtag_connect
=False)#True)
896 vl
= rtlil
.convert(top
, ports
=top
.ports())
897 with
open("test_jtag_blinker.il", "w") as f
:
901 # XXX these modules are all being added *AFTER* the build process links
902 # everything together. the expectation that this would work is...
903 # unrealistic. ordering, clearly, is important.
905 # This JTAG code copied from test, probably not needed
906 # dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
907 top
.jtag
.stop
= False
908 # rather than the client access the JTAG bus directly
909 # create an alternative that the client sets
912 cdut
.cbus
= JTAGInterface()
914 # set up client-server on port 44843-something
915 top
.jtag
.s
= JTAGServer()
916 cdut
.c
= JTAGClient()
917 top
.jtag
.s
.get_connection()
919 # print ("running server only as requested,
920 # use openocd remote to test")
922 # top.jtag.s.get_connection(None) # block waiting for connection
924 # take copy of ir_width and scan_len
925 cdut
._ir
_width
= top
.jtag
._ir
_width
926 cdut
.scan_len
= top
.jtag
.scan_len
928 p
= ASICPlatform (resources
, top
.jtag
)
930 # this is what needs to gets treated as "top", after "main module" top
931 # is augmented with IO pads with JTAG tacked on. the expectation that
932 # the get_input() etc functions will be called magically by some other
933 # function is unrealistic.
934 top_fragment
= p
.fragment
939 dut
= setup_blinker(build_blinker
=False)
941 # XXX simulating top (the module that does not itself contain IO pads
942 # because that's covered by build) cannot possibly be expected to work
943 # particularly when modules have been added *after* the platform build()
944 # function has been called.
947 sim
.add_clock(1e-6, domain
="sync") # standard clock
949 #sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
950 #if len(sys.argv) != 2 or sys.argv[1] != 'server':
952 #sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag)))
953 # handles (pretends to be) DMI
954 #sim.add_sync_process(wrap(dmi_sim(top.jtag)))
956 #sim.add_sync_process(wrap(test_gpios(top)))
957 #sim.add_sync_process(wrap(test_uart(top)))
958 #sim.add_sync_process(wrap(test_i2c(top)))
959 #sim.add_sync_process(wrap(test_debug_print()))
961 sim
.add_sync_process(wrap(test_jtag_bs_chain(dut
)))
963 with sim
.write_vcd("blinker_test.vcd"):
966 if __name__
== '__main__':