system/arm/bootloader/arm64/boot.S

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  */
  38
  39         .text
  40
  41         .globl  _start
  42 _start:
  43         /*
  44          * EL3 initialisation
  45          */
  46         mrs     x0, CurrentEL
  47         cmp     x0, #0xc                        // EL3?
  48         b.ne    start_ns                        // skip EL3 initialisation
  49
  50         mov     x0, #0x30                       // RES1
  51         orr     x0, x0, #(1 << 0)               // Non-secure EL1
  52         orr     x0, x0, #(1 << 8)               // HVC enable
  53         orr     x0, x0, #(1 << 10)              // 64-bit EL2
  54         msr     scr_el3, x0
  55
  56         msr     cptr_el3, xzr                   // Disable copro. traps to EL3
  57
  58         /*
  59          * Check for the primary CPU to avoid a race on the distributor
  60          * registers.
  61          */
  62         mrs     x0, mpidr_el1
  63         // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
  64         // Test the the MPIDR_EL1 register against 0xff00ffffff to
  65         // extract the primary CPU.
  66         ldr x1, =0xff00ffffff
  67 #ifdef GICV3
  68         and     x2, x0, #0xff // use Aff0 as cpuid for now...
  69         tst     x0, x1 // check for cpuid==zero
  70         b.ne    1f // secondary CPU
  71
  72         ldr     x1, =GIC_DIST_BASE // GICD_CTLR
  73         mov     w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
  74         str     w0, [x1]
  75
  76
  77 1:      ldr     x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
  78         // 128K for each redistributor, 256K strided...
  79         mov     x3, #1 << 18 // GICv4
  80         mul     x3, x3, x2
  81         add     x1, x1, x3
  82         mov     w0, #~0 // Grp1 interrupts
  83         str     w0, [x1], #4
  84         b.ne    2f // Only local interrupts for secondary CPUs
  85         ldr     x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
  86         str     w0, [x1], #4
  87         str     w0, [x1], #4
  88         str     w0, [x1], #4
  89
  90         /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
  91 2:      mrs     x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
  92         orr     x10, x10, #0xf      // enable 0xf
  93         msr     S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
  94         isb
  95
  96         mov     x0, #1
  97         msr     S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
  98         msr     S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
  99 #else
 100         tst x0, x1                    // check for cpuid==zero
 101         b.ne    1f                                    // secondary CPU
 102
 103         ldr     x1, =GIC_DIST_BASE              // GICD_CTLR
 104         mov     w0, #3                          // EnableGrp0 | EnableGrp1
 105         str     w0, [x1]
 106
 107 1:      ldr     x1, =GIC_DIST_BASE + 0x80       // GICD_IGROUPR
 108         mov     w0, #~0                         // Grp1 interrupts
 109         str     w0, [x1], #4
 110         b.ne    2f                              // Only local interrupts for secondary CPUs
 111         str     w0, [x1], #4
 112         str     w0, [x1], #4
 113
 114 2:      ldr     x1, =GIC_CPU_BASE               // GICC_CTLR
 115         ldr     w0, [x1]
 116         mov     w0, #3                          // EnableGrp0 | EnableGrp1
 117         str     w0, [x1]
 118
 119         mov     w0, #1 << 7                     // allow NS access to GICC_PMR
 120         str     w0, [x1, #4]                    // GICC_PMR
 121 #endif
 122
 123         msr     sctlr_el2, xzr
 124
 125         /*
 126          * Prepare the switch to the EL2_SP1 mode from EL3
 127          */
 128         ldr     x0, =start_ns                   // Return after mode switch
 129         mov     x1, #0x3c9                      // EL2_SP1 | D | A | I | F
 130         msr     elr_el3, x0
 131         msr     spsr_el3, x1
 132         eret
 133
 134 start_ns:
 135         /*
 136          * Kernel parameters
 137          */
 138         mov     x0, xzr
 139         mov     x1, xzr
 140         mov     x2, xzr
 141         mov     x3, xzr
 142
 143         mrs     x4, mpidr_el1
 144         // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
 145         // Test the the MPIDR_EL1 register against 0xff00ffffff to
 146         // extract the primary CPU.
 147         ldr x1, =0xff00ffffff
 148         tst x4, x1                    // check for cpuid==zero
 149         mov x1, xzr                   // load previous 'xzr' value back to x1
 150         b.eq    2f                                    // secondary CPU
 151
 152         /*
 153          * Secondary CPUs
 154          */
 155 1:      wfe
 156         ldr     x4, =PHYS_OFFSET + 0xfff8
 157         ldr     x4, [x4]
 158         cbz     x4, 1b
 159         br      x4                              // branch to the given address
 160
 161 2:
 162         /*
 163          * UART initialisation (38400 8N1)
 164          */
 165         ldr     x4, =UART_BASE                  // UART base
 166         mov     w5, #0x10                       // ibrd
 167         str     w5, [x4, #0x24]
 168         mov     w5, #0xc300
 169         orr     w5, w5, #0x0001                 // cr
 170         str     w5, [x4, #0x30]
 171
 172         /*
 173          * CLCD output site MB
 174          */
 175         ldr     x4, =SYSREGS_BASE
 176         ldr     w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16)      // START|WRITE|MUXFPGA|SITE_MB
 177         str     wzr, [x4, #0xa0]                // V2M_SYS_CFGDATA
 178         str     w5, [x4, #0xa4]                 // V2M_SYS_CFGCTRL
 179
 180         /*
 181          * Primary CPU
 182          */
 183         ldr     x0, =PHYS_OFFSET + 0x8000000     // device tree blob
 184         ldr     x6, =PHYS_OFFSET + 0x80000       // kernel start address
 185         br      x6
 186
 187         .ltorg
 188
 189         .org    0x200