techlibs/ecp5/cells_sim.v

   1 // ---------------------------------------
   2
   3 (* abc9_lut=1, lib_whitebox *)
   4 module LUT4(input A, B, C, D, output Z);
   5     parameter [15:0] INIT = 16'h0000;
   6     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
   7     wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
   8     wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
   9     assign Z =      A ?          s1[1] :         s1[0];
  10     specify
  11         (A => Z) = 141;
  12         (B => Z) = 275;
  13         (C => Z) = 379;
  14         (D => Z) = 379;
  15     endspecify
  16 endmodule
  17
  18 // This is a placeholder for ABC9 to extract the area/delay
  19 //   cost of 5-input LUTs and is not intended to be instantiated
  20 // LUT5 = 2x LUT4 + PFUMX
  21 (* abc9_lut=2 *)
  22 module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
  23     specify
  24         (M0 => Z) = 151;
  25         (D => Z) = 239;
  26         (C => Z) = 373;
  27         (B => Z) = 477;
  28         (A => Z) = 477;
  29     endspecify
  30 endmodule
  31
  32 // This is a placeholder for ABC9 to extract the area/delay
  33 //   of 6-input LUTs and is not intended to be instantiated
  34 // LUT6 = 2x LUT5 + MUX2
  35 (* abc9_lut=4 *)
  36 module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
  37     specify
  38         (M1 => Z) = 148;
  39         (M0 => Z) = 292;
  40         (D => Z) = 380;
  41         (C => Z) = 514;
  42         (B => Z) = 618;
  43         (A => Z) = 618;
  44     endspecify
  45 endmodule
  46
  47 // This is a placeholder for ABC9 to extract the area/delay
  48 //   of 7-input LUTs and is not intended to be instantiated
  49 // LUT7 = 2x LUT6 + MUX2
  50 (* abc9_lut=8 *)
  51 module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
  52     specify
  53         (M2 => Z) = 148;
  54         (M1 => Z) = 289;
  55         (M0 => Z) = 433;
  56         (D => Z) = 521;
  57         (C => Z) = 655;
  58         (B => Z) = 759;
  59         (A => Z) = 759;
  60     endspecify
  61 endmodule
  62
  63 // ---------------------------------------
  64 (* abc9_box, lib_whitebox *)
  65 module L6MUX21 (input D0, D1, SD, output Z);
  66         assign Z = SD ? D1 : D0;
  67         specify
  68                 (D0 => Z) = 140;
  69                 (D1 => Z) = 141;
  70                 (SD => Z) = 148;
  71         endspecify
  72 endmodule
  73
  74 // ---------------------------------------
  75 (* abc9_box, lib_whitebox *)
  76 module CCU2C(
  77         (* abc9_carry *)
  78         input  CIN,
  79         input  A0, B0, C0, D0, A1, B1, C1, D1,
  80         output S0, S1,
  81         (* abc9_carry *)
  82         output COUT
  83 );
  84         parameter [15:0] INIT0 = 16'h0000;
  85         parameter [15:0] INIT1 = 16'h0000;
  86         parameter INJECT1_0 = "YES";
  87         parameter INJECT1_1 = "YES";
  88
  89         // First half
  90         wire LUT4_0, LUT2_0;
  91         LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
  92         LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
  93         wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
  94         assign S0 = LUT4_0 ^ gated_cin_0;
  95
  96         wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
  97         wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
  98
  99         // Second half
 100         wire LUT4_1, LUT2_1;
 101         LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
 102         LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
 103         wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 104         assign S1 = LUT4_1 ^ gated_cin_1;
 105
 106         wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
 107         assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
 108
 109         specify
 110                 (A0 => S0) = 379;
 111                 (B0 => S0) = 379;
 112                 (C0 => S0) = 275;
 113                 (D0 => S0) = 141;
 114                 (CIN => S0) = 257;
 115                 (A0 => S1) = 630;
 116                 (B0 => S1) = 630;
 117                 (C0 => S1) = 526;
 118                 (D0 => S1) = 392;
 119                 (A1 => S1) = 379;
 120                 (B1 => S1) = 379;
 121                 (C1 => S1) = 275;
 122                 (D1 => S1) = 141;
 123                 (CIN => S1) = 273;
 124                 (A0 => COUT) = 516;
 125                 (B0 => COUT) = 516;
 126                 (C0 => COUT) = 412;
 127                 (D0 => COUT) = 278;
 128                 (A1 => COUT) = 516;
 129                 (B1 => COUT) = 516;
 130                 (C1 => COUT) = 412;
 131                 (D1 => COUT) = 278;
 132                 (CIN => COUT) = 43;
 133         endspecify
 134 endmodule
 135
 136 // ---------------------------------------
 137
 138 module TRELLIS_RAM16X2 (
 139         input DI0, DI1,
 140         input WAD0, WAD1, WAD2, WAD3,
 141         input WRE, WCK,
 142         input RAD0, RAD1, RAD2, RAD3,
 143         output DO0, DO1
 144 );
 145         parameter WCKMUX = "WCK";
 146         parameter WREMUX = "WRE";
 147         parameter INITVAL_0 = 16'h0000;
 148         parameter INITVAL_1 = 16'h0000;
 149
 150         reg [1:0] mem[15:0];
 151
 152         integer i;
 153         initial begin
 154                 for (i = 0; i < 16; i = i + 1)
 155                         mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
 156         end
 157
 158         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 159
 160         reg muxwre;
 161         always @(*)
 162                 case (WREMUX)
 163                         "1": muxwre = 1'b1;
 164                         "0": muxwre = 1'b0;
 165                         "INV": muxwre = ~WRE;
 166                         default: muxwre = WRE;
 167                 endcase
 168
 169
 170         always @(posedge muxwck)
 171                 if (muxwre)
 172                         mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
 173
 174         assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
 175 endmodule
 176
 177 // ---------------------------------------
 178 (* abc9_box, lib_whitebox *)
 179 module PFUMX (input ALUT, BLUT, C0, output Z);
 180         assign Z = C0 ? ALUT : BLUT;
 181         specify
 182                 (ALUT => Z) = 98;
 183                 (BLUT => Z) = 98;
 184                 (C0 => Z) = 151;
 185         endspecify
 186 endmodule
 187
 188 // ---------------------------------------
 189 (* abc9_box, lib_whitebox *)
 190 module TRELLIS_DPR16X4 (
 191         input  [3:0] DI,
 192         input  [3:0] WAD,
 193         input        WRE,
 194         input        WCK,
 195         input  [3:0] RAD,
 196         output [3:0] DO
 197 );
 198         parameter WCKMUX = "WCK";
 199         parameter WREMUX = "WRE";
 200         parameter [63:0] INITVAL = 64'h0000000000000000;
 201
 202         reg [3:0] mem[15:0];
 203
 204         integer i;
 205         initial begin
 206                 for (i = 0; i < 16; i = i + 1)
 207                         mem[i] <= INITVAL[4*i +: 4];
 208         end
 209
 210         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 211
 212         reg muxwre;
 213         always @(*)
 214                 case (WREMUX)
 215                         "1": muxwre = 1'b1;
 216                         "0": muxwre = 1'b0;
 217                         "INV": muxwre = ~WRE;
 218                         default: muxwre = WRE;
 219                 endcase
 220
 221         always @(posedge muxwck)
 222                 if (muxwre)
 223                         mem[WAD] <= DI;
 224
 225         assign DO = mem[RAD];
 226
 227         specify
 228                 // TODO
 229                 (RAD *> DO) = 0;
 230         endspecify
 231 endmodule
 232
 233 // ---------------------------------------
 234
 235 (* abc9_box, lib_whitebox *)
 236 module DPR16X4C (
 237                 input [3:0] DI,
 238                 input WCK, WRE,
 239                 input [3:0] RAD,
 240                 input [3:0] WAD,
 241                 output [3:0] DO
 242 );
 243         // For legacy Lattice compatibility, INITIVAL is a hex
 244         // string rather than a numeric parameter
 245         parameter INITVAL = "0x0000000000000000";
 246
 247         function [63:0] convert_initval;
 248                 input [143:0] hex_initval;
 249                 reg done;
 250                 reg [63:0] temp;
 251                 reg [7:0] char;
 252                 integer i;
 253                 begin
 254                         done = 1'b0;
 255                         temp = 0;
 256                         for (i = 0; i < 16; i = i + 1) begin
 257                                 if (!done) begin
 258                                         char = hex_initval[8*i +: 8];
 259                                         if (char == "x") begin
 260                                                 done = 1'b1;
 261                                         end else begin
 262                                                 if (char >= "0" && char <= "9")
 263                                                         temp[4*i +: 4] = char - "0";
 264                                                 else if (char >= "A" && char <= "F")
 265                                                         temp[4*i +: 4] = 10 + char - "A";
 266                                                 else if (char >= "a" && char <= "f")
 267                                                         temp[4*i +: 4] = 10 + char - "a";
 268                                         end
 269                                 end
 270                         end
 271                         convert_initval = temp;
 272                 end
 273         endfunction
 274
 275         localparam conv_initval = convert_initval(INITVAL);
 276
 277         reg [3:0] ram[0:15];
 278         integer i;
 279         initial begin
 280                 for (i = 0; i < 15; i = i + 1) begin
 281                         ram[i] <= conv_initval[4*i +: 4];
 282                 end
 283         end
 284
 285         always @(posedge WCK)
 286                 if (WRE)
 287                         ram[WAD] <= DI;
 288
 289         assign DO = ram[RAD];
 290
 291         specify
 292                 // TODO
 293                 (RAD *> DO) = 0;
 294         endspecify
 295 endmodule
 296
 297 // ---------------------------------------
 298
 299 (* lib_whitebox *)
 300 module LUT2(input A, B, output Z);
 301     parameter [3:0] INIT = 4'h0;
 302     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
 303     assign Z =      A ?          s1[1] :         s1[0];
 304 endmodule
 305
 306 // ---------------------------------------
 307
 308 `ifdef YOSYS
 309 (* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
 310 `endif
 311 module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 312         parameter GSR = "ENABLED";
 313         parameter [127:0] CEMUX = "1";
 314         parameter CLKMUX = "CLK";
 315         parameter LSRMUX = "LSR";
 316         parameter SRMODE = "LSR_OVER_CE";
 317         parameter REGSET = "RESET";
 318         parameter [127:0] LSRMODE = "LSR";
 319
 320         wire muxce;
 321         generate
 322                 case (CEMUX)
 323                         "1": assign muxce = 1'b1;
 324                         "0": assign muxce = 1'b0;
 325                         "INV": assign muxce = ~CE;
 326                         default: assign muxce = CE;
 327                 endcase
 328         endgenerate
 329
 330         wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 331         wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 332         wire srval;
 333         generate
 334                 if (LSRMODE == "PRLD")
 335                         assign srval = M;
 336                 else
 337                         assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 338         endgenerate
 339
 340         initial Q = srval;
 341
 342         generate
 343                 if (SRMODE == "ASYNC") begin
 344                         always @(posedge muxclk, posedge muxlsr)
 345                                 if (muxlsr)
 346                                         Q <= srval;
 347                                 else if (muxce)
 348                                         Q <= DI;
 349                 end else begin
 350                         always @(posedge muxclk)
 351                                 if (muxlsr)
 352                                         Q <= srval;
 353                                 else if (muxce)
 354                                         Q <= DI;
 355                 end
 356         endgenerate
 357
 358         specify
 359                 $setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
 360                 $setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
 361                 $setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
 362                 $setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
 363                 $setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
 364                 $setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
 365 `ifndef YOSYS
 366                 if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
 367                 if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
 368 `else
 369                 if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0;        // Technically, this should be an edge sensitive path
 370                                                                         // but for facilitating a bypass box, let's pretend it's
 371                                                                         // a simple path
 372 `endif
 373                 if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
 374                 if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
 375         endspecify
 376 endmodule
 377
 378 // ---------------------------------------
 379 (* keep *)
 380 module TRELLIS_IO(
 381         inout B,
 382         input I,
 383         input T,
 384         output O
 385 );
 386         parameter DIR = "INPUT";
 387         reg T_pd;
 388         always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 389
 390         generate
 391                 if (DIR == "INPUT") begin
 392                         assign B = 1'bz;
 393                         assign O = B;
 394                 end else if (DIR == "OUTPUT") begin
 395                         assign B = T_pd ? 1'bz : I;
 396                         assign O = 1'bx;
 397                 end else if (DIR == "BIDIR") begin
 398                         assign B = T_pd ? 1'bz : I;
 399                         assign O = B;
 400                 end else begin
 401                         ERROR_UNKNOWN_IO_MODE error();
 402                 end
 403         endgenerate
 404
 405 endmodule
 406
 407 // ---------------------------------------
 408
 409 module INV(input A, output Z);
 410         assign Z = !A;
 411 endmodule
 412
 413 // ---------------------------------------
 414
 415 module TRELLIS_SLICE(
 416         input A0, B0, C0, D0,
 417         input A1, B1, C1, D1,
 418         input M0, M1,
 419         input FCI, FXA, FXB,
 420
 421         input CLK, LSR, CE,
 422         input DI0, DI1,
 423
 424         input WD0, WD1,
 425         input WAD0, WAD1, WAD2, WAD3,
 426         input WRE, WCK,
 427
 428         output F0, Q0,
 429         output F1, Q1,
 430         output FCO, OFX0, OFX1,
 431
 432         output WDO0, WDO1, WDO2, WDO3,
 433         output WADO0, WADO1, WADO2, WADO3
 434 );
 435
 436         parameter MODE = "LOGIC";
 437         parameter GSR = "ENABLED";
 438         parameter SRMODE = "LSR_OVER_CE";
 439         parameter [127:0] CEMUX = "1";
 440         parameter CLKMUX = "CLK";
 441         parameter LSRMUX = "LSR";
 442         parameter LUT0_INITVAL = 16'h0000;
 443         parameter LUT1_INITVAL = 16'h0000;
 444         parameter REG0_SD = "0";
 445         parameter REG1_SD = "0";
 446         parameter REG0_REGSET = "RESET";
 447         parameter REG1_REGSET = "RESET";
 448         parameter REG0_LSRMODE = "LSR";
 449         parameter REG1_LSRMODE = "LSR";
 450         parameter [127:0] CCU2_INJECT1_0 = "NO";
 451         parameter [127:0] CCU2_INJECT1_1 = "NO";
 452         parameter WREMUX = "WRE";
 453         parameter WCKMUX = "WCK";
 454
 455         parameter A0MUX = "A0";
 456         parameter A1MUX = "A1";
 457         parameter B0MUX = "B0";
 458         parameter B1MUX = "B1";
 459         parameter C0MUX = "C0";
 460         parameter C1MUX = "C1";
 461         parameter D0MUX = "D0";
 462         parameter D1MUX = "D1";
 463
 464         wire A0m, B0m, C0m, D0m;
 465         wire A1m, B1m, C1m, D1m;
 466
 467         generate
 468                 if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
 469                 if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
 470                 if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
 471                 if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
 472                 if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
 473                 if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
 474                 if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
 475                 if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
 476
 477         endgenerate
 478
 479         function [15:0] permute_initval;
 480                 input [15:0] initval;
 481                 integer i;
 482                 begin
 483                         for (i = 0; i < 16; i = i + 1) begin
 484                                 permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
 485                         end
 486                 end
 487         endfunction
 488
 489         generate
 490                 if (MODE == "LOGIC") begin
 491                         // LUTs
 492                         LUT4 #(
 493                                 .INIT(LUT0_INITVAL)
 494                         ) lut4_0 (
 495                                 .A(A0m), .B(B0m), .C(C0m), .D(D0m),
 496                                 .Z(F0)
 497                         );
 498                         LUT4 #(
 499                                 .INIT(LUT1_INITVAL)
 500                         ) lut4_1 (
 501                                 .A(A1m), .B(B1m), .C(C1m), .D(D1m),
 502                                 .Z(F1)
 503                         );
 504                         // LUT expansion muxes
 505                         PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
 506                         L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
 507                 end else if (MODE == "CCU2") begin
 508                         CCU2C #(
 509                                 .INIT0(LUT0_INITVAL),
 510                                 .INIT1(LUT1_INITVAL),
 511                                 .INJECT1_0(CCU2_INJECT1_0),
 512                                 .INJECT1_1(CCU2_INJECT1_1)
 513                   ) ccu2c_i (
 514                                 .CIN(FCI),
 515                                 .A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
 516                                 .A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
 517                                 .S0(F0), .S1(F1),
 518                                 .COUT(FCO)
 519                         );
 520                 end else if (MODE == "RAMW") begin
 521                         assign WDO0 = C1m;
 522                         assign WDO1 = A1m;
 523                         assign WDO2 = D1m;
 524                         assign WDO3 = B1m;
 525                         assign WADO0 = D0m;
 526                         assign WADO1 = B0m;
 527                         assign WADO2 = C0m;
 528                         assign WADO3 = A0m;
 529                 end else if (MODE == "DPRAM") begin
 530                         TRELLIS_RAM16X2 #(
 531                                 .INITVAL_0(permute_initval(LUT0_INITVAL)),
 532                                 .INITVAL_1(permute_initval(LUT1_INITVAL)),
 533                                 .WREMUX(WREMUX)
 534                         ) ram_i (
 535                                 .DI0(WD0), .DI1(WD1),
 536                                 .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
 537                                 .WRE(WRE), .WCK(WCK),
 538                                 .RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
 539                                 .DO0(F0), .DO1(F1)
 540                         );
 541                         // TODO: confirm RAD and INITVAL ordering
 542                         // DPRAM mode contract?
 543 `ifdef FORMAL
 544                         always @(*) begin
 545                                 assert(A0m==A1m);
 546                                 assert(B0m==B1m);
 547                                 assert(C0m==C1m);
 548                                 assert(D0m==D1m);
 549                         end
 550 `endif
 551                 end else begin
 552                         ERROR_UNKNOWN_SLICE_MODE error();
 553                 end
 554         endgenerate
 555
 556         // FF input selection muxes
 557         wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
 558         wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
 559         // Flipflops
 560         TRELLIS_FF #(
 561                 .GSR(GSR),
 562                 .CEMUX(CEMUX),
 563                 .CLKMUX(CLKMUX),
 564                 .LSRMUX(LSRMUX),
 565                 .SRMODE(SRMODE),
 566                 .REGSET(REG0_REGSET),
 567                 .LSRMODE(REG0_LSRMODE)
 568         ) ff_0 (
 569                 .CLK(CLK), .LSR(LSR), .CE(CE),
 570                 .DI(muxdi0), .M(M0),
 571                 .Q(Q0)
 572         );
 573         TRELLIS_FF #(
 574                 .GSR(GSR),
 575                 .CEMUX(CEMUX),
 576                 .CLKMUX(CLKMUX),
 577                 .LSRMUX(LSRMUX),
 578                 .SRMODE(SRMODE),
 579                 .REGSET(REG1_REGSET),
 580                 .LSRMODE(REG1_LSRMODE)
 581         ) ff_1 (
 582                 .CLK(CLK), .LSR(LSR), .CE(CE),
 583                 .DI(muxdi1), .M(M1),
 584                 .Q(Q1)
 585         );
 586 endmodule
 587
 588 (* blackbox *)
 589 module DP16KD(
 590   input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
 591   input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
 592   input CEA, OCEA, CLKA, WEA, RSTA,
 593   input CSA2, CSA1, CSA0,
 594   output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
 595
 596   input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
 597   input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
 598   input CEB, OCEB, CLKB, WEB, RSTB,
 599   input CSB2, CSB1, CSB0,
 600   output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 601 );
 602         parameter DATA_WIDTH_A = 18;
 603         parameter DATA_WIDTH_B = 18;
 604
 605         parameter REGMODE_A = "NOREG";
 606         parameter REGMODE_B = "NOREG";
 607
 608         parameter RESETMODE = "SYNC";
 609         parameter ASYNC_RESET_RELEASE = "SYNC";
 610
 611         parameter CSDECODE_A = "0b000";
 612         parameter CSDECODE_B = "0b000";
 613
 614         parameter WRITEMODE_A = "NORMAL";
 615         parameter WRITEMODE_B = "NORMAL";
 616
 617         parameter DIA17MUX = "DIA17";
 618         parameter DIA16MUX = "DIA16";
 619         parameter DIA15MUX = "DIA15";
 620         parameter DIA14MUX = "DIA14";
 621         parameter DIA13MUX = "DIA13";
 622         parameter DIA12MUX = "DIA12";
 623         parameter DIA11MUX = "DIA11";
 624         parameter DIA10MUX = "DIA10";
 625         parameter DIA9MUX = "DIA9";
 626         parameter DIA8MUX = "DIA8";
 627         parameter DIA7MUX = "DIA7";
 628         parameter DIA6MUX = "DIA6";
 629         parameter DIA5MUX = "DIA5";
 630         parameter DIA4MUX = "DIA4";
 631         parameter DIA3MUX = "DIA3";
 632         parameter DIA2MUX = "DIA2";
 633         parameter DIA1MUX = "DIA1";
 634         parameter DIA0MUX = "DIA0";
 635         parameter ADA13MUX = "ADA13";
 636         parameter ADA12MUX = "ADA12";
 637         parameter ADA11MUX = "ADA11";
 638         parameter ADA10MUX = "ADA10";
 639         parameter ADA9MUX = "ADA9";
 640         parameter ADA8MUX = "ADA8";
 641         parameter ADA7MUX = "ADA7";
 642         parameter ADA6MUX = "ADA6";
 643         parameter ADA5MUX = "ADA5";
 644         parameter ADA4MUX = "ADA4";
 645         parameter ADA3MUX = "ADA3";
 646         parameter ADA2MUX = "ADA2";
 647         parameter ADA1MUX = "ADA1";
 648         parameter ADA0MUX = "ADA0";
 649         parameter CEAMUX = "CEA";
 650         parameter OCEAMUX = "OCEA";
 651         parameter CLKAMUX = "CLKA";
 652         parameter WEAMUX = "WEA";
 653         parameter RSTAMUX = "RSTA";
 654         parameter CSA2MUX = "CSA2";
 655         parameter CSA1MUX = "CSA1";
 656         parameter CSA0MUX = "CSA0";
 657         parameter DOA17MUX = "DOA17";
 658         parameter DOA16MUX = "DOA16";
 659         parameter DOA15MUX = "DOA15";
 660         parameter DOA14MUX = "DOA14";
 661         parameter DOA13MUX = "DOA13";
 662         parameter DOA12MUX = "DOA12";
 663         parameter DOA11MUX = "DOA11";
 664         parameter DOA10MUX = "DOA10";
 665         parameter DOA9MUX = "DOA9";
 666         parameter DOA8MUX = "DOA8";
 667         parameter DOA7MUX = "DOA7";
 668         parameter DOA6MUX = "DOA6";
 669         parameter DOA5MUX = "DOA5";
 670         parameter DOA4MUX = "DOA4";
 671         parameter DOA3MUX = "DOA3";
 672         parameter DOA2MUX = "DOA2";
 673         parameter DOA1MUX = "DOA1";
 674         parameter DOA0MUX = "DOA0";
 675         parameter DIB17MUX = "DIB17";
 676         parameter DIB16MUX = "DIB16";
 677         parameter DIB15MUX = "DIB15";
 678         parameter DIB14MUX = "DIB14";
 679         parameter DIB13MUX = "DIB13";
 680         parameter DIB12MUX = "DIB12";
 681         parameter DIB11MUX = "DIB11";
 682         parameter DIB10MUX = "DIB10";
 683         parameter DIB9MUX = "DIB9";
 684         parameter DIB8MUX = "DIB8";
 685         parameter DIB7MUX = "DIB7";
 686         parameter DIB6MUX = "DIB6";
 687         parameter DIB5MUX = "DIB5";
 688         parameter DIB4MUX = "DIB4";
 689         parameter DIB3MUX = "DIB3";
 690         parameter DIB2MUX = "DIB2";
 691         parameter DIB1MUX = "DIB1";
 692         parameter DIB0MUX = "DIB0";
 693         parameter ADB13MUX = "ADB13";
 694         parameter ADB12MUX = "ADB12";
 695         parameter ADB11MUX = "ADB11";
 696         parameter ADB10MUX = "ADB10";
 697         parameter ADB9MUX = "ADB9";
 698         parameter ADB8MUX = "ADB8";
 699         parameter ADB7MUX = "ADB7";
 700         parameter ADB6MUX = "ADB6";
 701         parameter ADB5MUX = "ADB5";
 702         parameter ADB4MUX = "ADB4";
 703         parameter ADB3MUX = "ADB3";
 704         parameter ADB2MUX = "ADB2";
 705         parameter ADB1MUX = "ADB1";
 706         parameter ADB0MUX = "ADB0";
 707         parameter CEBMUX = "CEB";
 708         parameter OCEBMUX = "OCEB";
 709         parameter CLKBMUX = "CLKB";
 710         parameter WEBMUX = "WEB";
 711         parameter RSTBMUX = "RSTB";
 712         parameter CSB2MUX = "CSB2";
 713         parameter CSB1MUX = "CSB1";
 714         parameter CSB0MUX = "CSB0";
 715         parameter DOB17MUX = "DOB17";
 716         parameter DOB16MUX = "DOB16";
 717         parameter DOB15MUX = "DOB15";
 718         parameter DOB14MUX = "DOB14";
 719         parameter DOB13MUX = "DOB13";
 720         parameter DOB12MUX = "DOB12";
 721         parameter DOB11MUX = "DOB11";
 722         parameter DOB10MUX = "DOB10";
 723         parameter DOB9MUX = "DOB9";
 724         parameter DOB8MUX = "DOB8";
 725         parameter DOB7MUX = "DOB7";
 726         parameter DOB6MUX = "DOB6";
 727         parameter DOB5MUX = "DOB5";
 728         parameter DOB4MUX = "DOB4";
 729         parameter DOB3MUX = "DOB3";
 730         parameter DOB2MUX = "DOB2";
 731         parameter DOB1MUX = "DOB1";
 732         parameter DOB0MUX = "DOB0";
 733
 734         parameter WID = 0;
 735
 736         parameter GSR = "ENABLED";
 737
 738         parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 739         parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 740         parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 741         parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 742         parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 743         parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 744         parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 745         parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 746         parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 747         parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 748         parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 749         parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 750         parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 751         parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 752         parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 753         parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 754         parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 755         parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 756         parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 757         parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 758         parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 759         parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 760         parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 761         parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 762         parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 763         parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 764         parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 765         parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 766         parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 767         parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 768         parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 769         parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 770         parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 771         parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 772         parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 773         parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 774         parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 775         parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 776         parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 777         parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 778         parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 779         parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 780         parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 781         parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 782         parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 783         parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 784         parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 785         parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 786         parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 787         parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 788         parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 789         parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 790         parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 791         parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 792         parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 793         parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 794         parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 795         parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 796         parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 797         parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 798         parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 799         parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 800         parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 801         parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 802 endmodule
 803
 804 `ifndef NO_INCLUDES
 805
 806 `include "cells_ff.vh"
 807 `include "cells_io.vh"
 808
 809 `endif