tercel/wishbone_spi_master.v

   1 // © 2017 - 2022 Raptor Engineering, LLC
   2 //
   3 // Released under the terms of the GNU LGPL v3
   4 // See the LICENSE file for full details
   5
   6 // =============================================================================================
   7 // Memory Map:
   8 // =============================================================================================
   9 // Device ID string (8 bytes)
  10 // Device version (4 bytes)
  11 // Base clock frequency (4 bytes)
  12 // PHY configuration register 1 (4 bytes): {cs_extra_idle_cycles, 2'b0, qspi_write_quad_io_en, qspi_read_quad_io_en, fast_read_mode, four_byte_address_mode, phy_io_type, dummy_cycle_count, spi_clock_divisor}
  13 // Flash configuration register 1 (4 bytes): {4BA QSPI read command, 3BA QSPI read command, 4BA SPI read command, 3BA SPI read command}
  14 // Flash configuration register 2 (4 bytes): {4BA QSPI fast read command, 3BA QSPI fast read command, 4BA SPI fast read command, 3BA SPI fast read command}
  15 // Flash configuration register 3 (4 bytes): {4BA QSPI program command, 3BA QSPI program command, 4BA SPI program command, 3BA SPI program command}
  16 // Flash configuration register 4 (4 bytes): {spi_cs_active_hold_cycles}
  17 // Flash configuration register 5 (4 bytes): {30'b0, allow_multicycle_writes, allow_multicycle_reads}
  18 // Control register 1 (4 bytes): {31'b0, user_command_mode}
  19 // Data register 1 (4 bytes): {24'b0, user_command_mode_read_during_write}
  20
  21 // Stop LiteX silently ignoring net naming / missing register errors
  22 `default_nettype none
  23
  24 module tercel_core(
  25                 // Configuration registers
  26                 input wire [31:0] sys_clk_freq,
  27
  28                 // Wishbone signals
  29                 input wire wishbone_cyc,
  30                 input wire wishbone_stb,
  31                 input wire wishbone_we,
  32                 input wire [29:0] wishbone_adr,
  33                 input wire [31:0] wishbone_dat_w,
  34                 output wire [31:0] wishbone_dat_r,
  35                 input wire [3:0] wishbone_sel,
  36                 output wire wishbone_ack,
  37                 output wire wishbone_err,
  38
  39                 // Wishbone configuration port signals
  40                 input wire cfg_wishbone_cyc,
  41                 input wire cfg_wishbone_stb,
  42                 input wire cfg_wishbone_we,
  43                 input wire [29:0] cfg_wishbone_adr,
  44                 input wire [31:0] cfg_wishbone_dat_w,
  45                 output wire [31:0] cfg_wishbone_dat_r,
  46                 input wire [3:0] cfg_wishbone_sel,
  47                 output wire cfg_wishbone_ack,
  48                 output wire cfg_wishbone_err,
  49
  50                 // SPI bus signals
  51                 output wire spi_clock,
  52                 output wire [3:0] spi_d_out,
  53                 output wire [3:0] spi_d_direction,                      // 0 == tristate (input), 1 == driven (output)
  54                 input wire [3:0] spi_d_in,
  55                 output wire spi_ss_n,
  56
  57                 output wire [7:0] debug_port,
  58
  59                 input wire peripheral_reset,
  60                 input wire peripheral_clock
  61         );
  62
  63         // Control and status registers
  64         wire [63:0] device_id;
  65         wire [31:0] device_version;
  66
  67         // PHY configuration register 1
  68         // Defaults to Quad SPI mode, 3BA,
  69     // non-extended read/write (qspi_[read|write]_quad_io_en = 0),
  70     // cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16
  71         reg [31:0] phy_cfg1 = 32'h00020a10;
  72
  73         // Defaults to compatibility with Micron N25Q/512MB and similar 3BA/4BA capable devices, with multicycle and write disabled
  74         // Note that the N25Q does not support normal reads in QSPI mode, so we leave the QSPI normal read commands equal
  75         // to the normal SPI commands for safety -- no corruption is possible if the device is latched into read mode...
  76         reg [31:0] flash_cfg1 = 32'h13031303;
  77         reg [31:0] flash_cfg2 = 32'heceb0c0b;
  78         reg [31:0] flash_cfg3 = 32'h34321202;
  79         reg [31:0] flash_cfg4 = 32'h00000000;
  80         reg [31:0] flash_cfg5 = 32'h00000000;
  81
  82         // Defaults to read mode
  83         reg [31:0] core_ctl1 = 32'h00000000;
  84         wire [31:0] core_data1;
  85
  86         // Device identifier
  87         assign device_id = 64'h7c5250545350494d;
  88         assign device_version = 32'h00010000;
  89
  90         reg cfg_wishbone_ack_reg = 0;
  91         reg [31:0] cfg_wishbone_dat_r_reg = 0;
  92
  93         assign cfg_wishbone_ack = cfg_wishbone_ack_reg;
  94         assign cfg_wishbone_dat_r = cfg_wishbone_dat_r_reg;
  95
  96         parameter WB_CFG_TRANSFER_STATE_IDLE = 0;
  97         parameter WB_CFG_TRANSFER_STATE_TR01 = 1;
  98
  99         reg [31:0] wishbone_config_buffer_address_reg = 0;
 100         reg [7:0] wishbone_config_transfer_state = 0;
 101         reg [31:0] wishbone_cfg_space_tx_buffer = 0;
 102         reg [31:0] wishbone_cfg_space_rx_buffer = 0;
 103
 104         // Wishbone configuration space connector
 105         always @(posedge peripheral_clock) begin
 106                 if (peripheral_reset) begin
 107                         // Reset Wishbone interface / control state machine
 108                         cfg_wishbone_ack_reg <= 0;
 109
 110                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 111                 end else begin
 112                         case (wishbone_config_transfer_state)
 113                                 WB_CFG_TRANSFER_STATE_IDLE: begin
 114                                         // Compute effective address
 115                                         wishbone_config_buffer_address_reg[31:2] = cfg_wishbone_adr;
 116                                         case (cfg_wishbone_sel)
 117                                                 4'b0001: wishbone_config_buffer_address_reg[1:0] = 0;
 118                                                 4'b0010: wishbone_config_buffer_address_reg[1:0] = 1;
 119                                                 4'b0100: wishbone_config_buffer_address_reg[1:0] = 2;
 120                                                 4'b1000: wishbone_config_buffer_address_reg[1:0] = 3;
 121                                                 4'b1111: wishbone_config_buffer_address_reg[1:0] = 0;
 122                                                 default: wishbone_config_buffer_address_reg[1:0] = 0;
 123                                         endcase
 124
 125                                         if (cfg_wishbone_cyc && cfg_wishbone_stb) begin
 126                                                 // Configuration register space access
 127                                                 // Single clock pulse signals in deasserted state...process incoming request!
 128                                                 if (!cfg_wishbone_we) begin
 129                                                         // Read requested
 130                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 131                                                                 0: wishbone_cfg_space_tx_buffer = device_id[63:32];
 132                                                                 4: wishbone_cfg_space_tx_buffer = device_id[31:0];
 133                                                                 8: wishbone_cfg_space_tx_buffer = device_version;
 134                                                                 12: wishbone_cfg_space_tx_buffer = sys_clk_freq;
 135                                                                 16: wishbone_cfg_space_tx_buffer = phy_cfg1;
 136                                                                 20: wishbone_cfg_space_tx_buffer = flash_cfg1;
 137                                                                 24: wishbone_cfg_space_tx_buffer = flash_cfg2;
 138                                                                 28: wishbone_cfg_space_tx_buffer = flash_cfg3;
 139                                                                 32: wishbone_cfg_space_tx_buffer = flash_cfg4;
 140                                                                 36: wishbone_cfg_space_tx_buffer = flash_cfg5;
 141                                                                 40: wishbone_cfg_space_tx_buffer = core_ctl1;
 142                                                                 44: wishbone_cfg_space_tx_buffer = core_data1;
 143                                                                 default: wishbone_cfg_space_tx_buffer = 0;
 144                                                         endcase
 145
 146                                                         // Endian swap
 147                                                         cfg_wishbone_dat_r_reg[31:24] <= wishbone_cfg_space_tx_buffer[7:0];
 148                                                         cfg_wishbone_dat_r_reg[23:16] <= wishbone_cfg_space_tx_buffer[15:8];
 149                                                         cfg_wishbone_dat_r_reg[15:8] <= wishbone_cfg_space_tx_buffer[23:16];
 150                                                         cfg_wishbone_dat_r_reg[7:0] <= wishbone_cfg_space_tx_buffer[31:24];
 151
 152                                                         // Signal transfer complete
 153                                                         cfg_wishbone_ack_reg <= 1;
 154
 155                                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_TR01;
 156                                                 end else begin
 157                                                         // Write requested
 158                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 159                                                                 // Device ID / version registers cannot be written, don't even try...
 160                                                                 16: wishbone_cfg_space_rx_buffer = phy_cfg1;
 161                                                                 20: wishbone_cfg_space_rx_buffer = flash_cfg1;
 162                                                                 24: wishbone_cfg_space_rx_buffer = flash_cfg2;
 163                                                                 28: wishbone_cfg_space_rx_buffer = flash_cfg3;
 164                                                                 32: wishbone_cfg_space_rx_buffer = flash_cfg4;
 165                                                                 36: wishbone_cfg_space_rx_buffer = flash_cfg5;
 166                                                                 40: wishbone_cfg_space_rx_buffer = core_ctl1;
 167                                                                 // Status registers cannot be written, don't even try...
 168                                                                 default: wishbone_cfg_space_rx_buffer = 0;
 169                                                         endcase
 170
 171                                                         if (cfg_wishbone_sel[0]) begin
 172                                                                 wishbone_cfg_space_rx_buffer[7:0] = cfg_wishbone_dat_w[31:24];
 173                                                         end
 174                                                         if (cfg_wishbone_sel[1]) begin
 175                                                                 wishbone_cfg_space_rx_buffer[15:8] = cfg_wishbone_dat_w[23:16];
 176                                                         end
 177                                                         if (cfg_wishbone_sel[2]) begin
 178                                                                 wishbone_cfg_space_rx_buffer[23:16] = cfg_wishbone_dat_w[15:8];
 179                                                         end
 180                                                         if (cfg_wishbone_sel[3]) begin
 181                                                                 wishbone_cfg_space_rx_buffer[31:24] = cfg_wishbone_dat_w[7:0];
 182                                                         end
 183
 184                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 185                                                                 16: phy_cfg1 <= wishbone_cfg_space_rx_buffer;
 186                                                                 20: flash_cfg1 <= wishbone_cfg_space_rx_buffer;
 187                                                                 24: flash_cfg2 <= wishbone_cfg_space_rx_buffer;
 188                                                                 28: flash_cfg3 <= wishbone_cfg_space_rx_buffer;
 189                                                                 32: flash_cfg4 <= wishbone_cfg_space_rx_buffer;
 190                                                                 36: flash_cfg5 <= wishbone_cfg_space_rx_buffer;
 191                                                                 40: core_ctl1 <= wishbone_cfg_space_rx_buffer;
 192                                                         endcase
 193
 194                                                         // Signal transfer complete
 195                                                         cfg_wishbone_ack_reg <= 1;
 196
 197                                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_TR01;
 198                                                 end
 199                                         end
 200                                 end
 201                                 WB_CFG_TRANSFER_STATE_TR01: begin
 202                                         // Cycle complete
 203                                         cfg_wishbone_ack_reg <= 0;
 204                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 205                                 end
 206                                 default: begin
 207                                         // Should never reach this state
 208                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 209                                 end
 210                         endcase
 211                 end
 212         end
 213
 214         // SPI bus signals
 215         wire spi_data_direction;
 216         wire spi_quad_mode_pin_enable;
 217         wire drive_host_interfaces;
 218         assign drive_host_interfaces = 1;
 219         assign spi_d_direction[0] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 220         assign spi_d_direction[1] = spi_quad_mode_pin_enable && (spi_data_direction & drive_host_interfaces);
 221         assign spi_d_direction[2] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 222         assign spi_d_direction[3] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 223
 224         // Interface registers
 225         wire [7:0] spi_clock_divisor;
 226         wire [7:0] dummy_cycle_count;
 227         wire [1:0] phy_io_type;
 228         wire [7:0] cs_extra_idle_cycles;
 229         wire four_byte_address_mode;
 230         wire fast_read_mode;
 231         wire qspi_read_quad_io_en;
 232         wire qspi_write_quad_io_en;
 233         wire [7:0] qspi_read_4ba_command_code;
 234         wire [7:0] qspi_read_3ba_command_code;
 235         wire [7:0] spi_read_4ba_command_code;
 236         wire [7:0] spi_read_3ba_command_code;
 237         wire [7:0] qspi_fast_read_4ba_command_code;
 238         wire [7:0] qspi_fast_read_3ba_command_code;
 239         wire [7:0] spi_fast_read_4ba_command_code;
 240         wire [7:0] spi_fast_read_3ba_command_code;
 241         wire [7:0] qspi_program_4ba_command_code;
 242         wire [7:0] qspi_program_3ba_command_code;
 243         wire [7:0] spi_program_4ba_command_code;
 244         wire [7:0] spi_program_3ba_command_code;
 245         wire [31:0] spi_cs_active_hold_cycles;
 246         wire allow_multicycle_writes;
 247         wire allow_multicycle_reads;
 248         wire user_command_mode;
 249         reg [7:0] user_command_mode_read_during_write = 0;
 250         assign spi_clock_divisor = phy_cfg1[7:0];
 251         assign dummy_cycle_count = phy_cfg1[15:8];
 252         assign phy_io_type = phy_cfg1[17:16];
 253         assign cs_extra_idle_cycles = phy_cfg1[31:24];
 254         assign four_byte_address_mode = phy_cfg1[18];
 255         assign fast_read_mode = phy_cfg1[19];
 256         assign qspi_read_quad_io_en = phy_cfg1[20];
 257         assign qspi_write_quad_io_en = phy_cfg1[21];
 258         assign qspi_read_4ba_command_code = flash_cfg1[31:24];
 259         assign qspi_read_3ba_command_code = flash_cfg1[23:16];
 260         assign spi_read_4ba_command_code = flash_cfg1[15:8];
 261         assign spi_read_3ba_command_code = flash_cfg1[7:0];
 262         assign qspi_fast_read_4ba_command_code = flash_cfg2[31:24];
 263         assign qspi_fast_read_3ba_command_code = flash_cfg2[23:16];
 264         assign spi_fast_read_4ba_command_code = flash_cfg2[15:8];
 265         assign spi_fast_read_3ba_command_code = flash_cfg2[7:0];
 266         assign qspi_program_4ba_command_code = flash_cfg3[31:24];
 267         assign qspi_program_3ba_command_code = flash_cfg3[23:16];
 268         assign spi_program_4ba_command_code = flash_cfg3[15:8];
 269         assign spi_program_3ba_command_code = flash_cfg3[7:0];
 270         assign spi_cs_active_hold_cycles = flash_cfg4[31:0];
 271         assign allow_multicycle_writes = flash_cfg5[1];
 272         assign allow_multicycle_reads = flash_cfg5[0];
 273         assign user_command_mode = core_ctl1[0];
 274         assign core_data1 = {24'h000000, user_command_mode_read_during_write};
 275
 276         parameter PHY_IO_TYPE_SINGLE = 0;
 277         parameter PHY_IO_TYPE_QUAD = 2;
 278
 279         // PHY clock generator
 280         // Divisor:
 281         // (spi_clock_divisor - 1) * 2
 282         // 0 == undefined (actually divide by two)
 283         // 1 == divide by 1
 284         // 2 == divide by 2
 285         // 3 == divide by 4
 286         // 4 == divide by 6
 287         // 5 == divide by 8
 288         // 6 == divide by 10
 289         // 7 == divide by 12
 290         // etc.
 291         wire spi_phy_clock;
 292         reg spi_phy_clock_gen_reg = 0;
 293         reg [7:0] spi_phy_clock_counter = 0;
 294         assign spi_phy_clock = (spi_clock_divisor == 1)?peripheral_clock:spi_phy_clock_gen_reg;
 295         always @(posedge peripheral_clock) begin
 296                 if (spi_phy_clock_counter >= (spi_clock_divisor - 2)) begin
 297                         spi_phy_clock_gen_reg <= ~spi_phy_clock_gen_reg;
 298                         spi_phy_clock_counter <= 0;
 299                 end else begin
 300                         spi_phy_clock_counter <= spi_phy_clock_counter + 1;
 301                 end
 302         end
 303
 304         reg [31:0] phy_tx_data = 0;
 305         wire [31:0] phy_rx_data;
 306         reg phy_hold_ss_active = 0;
 307         reg phy_qspi_mode_active = 0;
 308         reg phy_qspi_transfer_mode = 0;
 309         reg phy_qspi_transfer_direction = 0;
 310         reg [7:0] phy_dummy_cycle_count = 0;
 311         reg [3:0] single_cycle_read_counter = 0;
 312         reg [3:0] single_cycle_write_counter = 0;
 313         reg phy_cycle_start = 0;
 314         wire phy_transaction_complete;
 315
 316         spi_master_phy_quad spi_master_phy_quad(
 317                 .platform_clock(spi_phy_clock),
 318                 .reset(peripheral_reset),
 319                 .tx_data(phy_tx_data),
 320                 .rx_data(phy_rx_data),
 321                 .dummy_cycle_count(phy_dummy_cycle_count),
 322                 .hold_ss_active(phy_hold_ss_active),
 323                 .qspi_mode_active(phy_qspi_mode_active),
 324                 .qspi_transfer_mode(phy_qspi_transfer_mode),
 325                 .qspi_transfer_direction(phy_qspi_transfer_direction),
 326                 .cycle_start(phy_cycle_start),
 327                 .transaction_complete(phy_transaction_complete),
 328
 329                 .spi_clock(spi_clock),
 330                 .spi_d0_out(spi_d_out[0]),
 331                 .spi_d0_in(spi_d_in[0]),
 332                 .spi_d1_out(spi_d_out[1]),
 333                 .spi_d1_in(spi_d_in[1]),
 334                 .spi_d2_out(spi_d_out[2]),
 335                 .spi_d2_in(spi_d_in[2]),
 336                 .spi_d3_out(spi_d_out[3]),
 337                 .spi_d3_in(spi_d_in[3]),
 338                 .spi_ss_n(spi_ss_n),
 339                 .spi_data_direction(spi_data_direction),
 340                 .spi_quad_mode_pin_enable(spi_quad_mode_pin_enable)
 341         );
 342
 343         reg [3:0] wishbone_sel_reg = 0;
 344         reg wishbone_ack_reg = 0;
 345         assign wishbone_ack = wishbone_ack_reg;
 346         reg [31:0] wishbone_dat_r_reg = 0;
 347         assign wishbone_dat_r = wishbone_dat_r_reg;
 348
 349         parameter SPI_MASTER_TRANSFER_STATE_IDLE = 0;
 350         parameter SPI_MASTER_TRANSFER_STATE_TR01 = 1;
 351         parameter SPI_MASTER_TRANSFER_STATE_TR02 = 2;
 352         parameter SPI_MASTER_TRANSFER_STATE_TR03 = 16;
 353         parameter SPI_MASTER_TRANSFER_STATE_TR04 = 17;
 354         parameter SPI_MASTER_TRANSFER_STATE_TR05 = 18;
 355         parameter SPI_MASTER_TRANSFER_STATE_TR06 = 19;
 356         parameter SPI_MASTER_TRANSFER_STATE_TR07 = 20;
 357         parameter SPI_MASTER_TRANSFER_STATE_TR08 = 21;
 358         parameter SPI_MASTER_TRANSFER_STATE_TR09 = 22;
 359         parameter SPI_MASTER_TRANSFER_STATE_TR10 = 23;
 360         parameter SPI_MASTER_TRANSFER_STATE_TR11 = 24;
 361         parameter SPI_MASTER_TRANSFER_STATE_TR12 = 25;
 362         parameter SPI_MASTER_TRANSFER_STATE_RD01 = 32;
 363         parameter SPI_MASTER_TRANSFER_STATE_RD02 = 33;
 364         parameter SPI_MASTER_TRANSFER_STATE_RD03 = 34;
 365         parameter SPI_MASTER_TRANSFER_STATE_WR01 = 48;
 366         parameter SPI_MASTER_TRANSFER_STATE_WR02 = 49;
 367         parameter SPI_MASTER_TRANSFER_STATE_WR03 = 50;
 368         parameter SPI_MASTER_TRANSFER_STATE_UC01 = 64;
 369         parameter SPI_MASTER_TRANSFER_STATE_UC02 = 65;
 370         parameter SPI_MASTER_TRANSFER_STATE_UC03 = 66;
 371         parameter SPI_MASTER_TRANSFER_STATE_UC04 = 67;
 372
 373         reg [7:0] byte_out = 0;
 374         reg [7:0] spi_transfer_state = 0;
 375         reg spi_data_cycle_type = 0;
 376         reg [31:0] spi_address_reg = 0;
 377         reg [1:0] phy_io_type_reg;
 378         reg [31:0] spi_byte_read_count = 0;
 379         reg wishbone_data_cycle_type = 0;
 380         reg wishbone_access_is_32_bits = 0;
 381         reg user_command_mode_active = 0;
 382         reg multicycle_read_in_progress = 0;
 383         reg multicycle_write_in_progress = 0;
 384         reg [31:0] multicycle_transaction_address = 0;
 385         reg [7:0] cs_extra_cycle_counter = 0;
 386         reg [31:0] spi_cs_active_counter = 0;
 387
 388         assign debug_port = spi_transfer_state;
 389
 390         always @(posedge peripheral_clock) begin
 391                 if (peripheral_reset) begin
 392                         // Reset PHY
 393                         phy_hold_ss_active <= 0;
 394                         phy_qspi_mode_active <= 0;
 395                         phy_qspi_transfer_mode <= 0;
 396                         phy_qspi_transfer_direction <= 0;
 397                         phy_dummy_cycle_count <= 0;
 398                         phy_cycle_start <= 0;
 399
 400                         // Reset Wishbone interface / control state machine
 401                         wishbone_ack_reg <= 0;
 402                         wishbone_data_cycle_type <= 0;
 403                         wishbone_access_is_32_bits <= 0;
 404                         user_command_mode_read_during_write <= 0;
 405                         user_command_mode_active <= 0;
 406                         multicycle_read_in_progress <= 0;
 407                         multicycle_write_in_progress <= 0;
 408                         multicycle_transaction_address <= 0;
 409                         spi_cs_active_counter <= 0;
 410                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 411                 end else begin
 412                         case (spi_transfer_state)
 413                                 SPI_MASTER_TRANSFER_STATE_IDLE: begin
 414                                         // Compute effective address
 415                                         spi_address_reg[31:2] = wishbone_adr;
 416                                         case (wishbone_sel)
 417                                                 4'b0001: spi_address_reg[1:0] = 0;
 418                                                 4'b0010: spi_address_reg[1:0] = 1;
 419                                                 4'b0100: spi_address_reg[1:0] = 2;
 420                                                 4'b1000: spi_address_reg[1:0] = 3;
 421                                                 4'b1111: spi_address_reg[1:0] = 0;
 422                                                 default: spi_address_reg[1:0] = 0;
 423                                         endcase
 424
 425                                         // Process command
 426                                         if ((spi_cs_active_hold_cycles > 0) && (spi_cs_active_counter >= spi_cs_active_hold_cycles)) begin
 427                                                 // Stop multicycle transfer
 428                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 429                                         end else if (!user_command_mode && user_command_mode_active) begin
 430                                                 // Exit user command mode
 431                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 432                                         end else if (multicycle_read_in_progress) begin
 433                                                 if (!allow_multicycle_reads) begin
 434                                                         // Stop multicycle transfer
 435                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 436                                                 end else if (wishbone_cyc && wishbone_stb) begin
 437                                                         if (user_command_mode) begin
 438                                                                 // User command mode requested
 439                                                                 // Stop multicycle transfer in preparation to enable user command mode
 440                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 441                                                         end else if (wishbone_data_cycle_type) begin
 442                                                                 // Write requested
 443                                                                 // Stop multicycle transfer in preparation to enable write mode
 444                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 445                                                         end else begin
 446                                                                 // Select 8-bit/32-bit transfer size via Wishbone access mode
 447                                                                 if (wishbone_sel == 4'b1111) begin
 448                                                                         wishbone_access_is_32_bits <= 1;
 449                                                                 end else begin
 450                                                                         wishbone_access_is_32_bits <= 0;
 451                                                                 end
 452                                                                 wishbone_sel_reg <= wishbone_sel;
 453
 454                                                                 // Verify next address matches current address
 455                                                                 if (four_byte_address_mode) begin
 456                                                                         if (multicycle_transaction_address == spi_address_reg) begin
 457                                                                                 // Transfer next data chunk
 458                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 459                                                                         end else begin
 460                                                                                 // Stop multicycle transfer
 461                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 462                                                                         end
 463                                                                 end else begin
 464                                                                         if (multicycle_transaction_address[23:0] == spi_address_reg[23:0]) begin
 465                                                                                 // Transfer next data chunk
 466                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 467                                                                         end else begin
 468                                                                                 // Stop multicycle transfer
 469                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 470                                                                         end
 471                                                                 end
 472                                                         end
 473                                                 end
 474                                         end else if (multicycle_write_in_progress) begin
 475                                                 if (!allow_multicycle_writes) begin
 476                                                         // Stop multicycle transfer
 477                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 478                                                 end else if (wishbone_cyc && wishbone_stb) begin
 479                                                         if (user_command_mode) begin
 480                                                                 // User command mode requested
 481                                                                 // Stop multicycle transfer in preparation to enable user command mode
 482                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 483                                                         end else if (!wishbone_data_cycle_type) begin
 484                                                                 // Read requested
 485                                                                 // Stop multicycle transfer in preparation to enable read mode
 486                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 487                                                         end else begin
 488                                                                 // Select 8-bit/32-bit transfer size via Wishbone access mode
 489                                                                 if (wishbone_sel == 4'b1111) begin
 490                                                                         wishbone_access_is_32_bits <= 1;
 491                                                                 end else begin
 492                                                                         wishbone_access_is_32_bits <= 0;
 493                                                                 end
 494                                                                 wishbone_sel_reg <= wishbone_sel;
 495
 496                                                                 // Verify next address matches current address
 497                                                                 if (four_byte_address_mode) begin
 498                                                                         if (multicycle_transaction_address == spi_address_reg) begin
 499                                                                                 // Transfer next data chunk
 500                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 501                                                                         end else begin
 502                                                                                 // Stop multicycle transfer
 503                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 504                                                                         end
 505                                                                 end else begin
 506                                                                         if (multicycle_transaction_address[23:0] == spi_address_reg[23:0]) begin
 507                                                                                 // Transfer next data chunk
 508                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 509                                                                         end else begin
 510                                                                                 // Stop multicycle transfer
 511                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 512                                                                         end
 513                                                                 end
 514                                                         end
 515                                                 end
 516                                         end else begin
 517                                                 if (wishbone_cyc && wishbone_stb) begin
 518                                                         if (wishbone_sel == 4'b1111) begin
 519                                                                 wishbone_access_is_32_bits <= 1;
 520                                                         end else begin
 521                                                                 wishbone_access_is_32_bits <= 0;
 522                                                         end
 523                                                         wishbone_sel_reg <= wishbone_sel;
 524                                                         wishbone_data_cycle_type <= wishbone_we;
 525                                                         phy_io_type_reg <= phy_io_type;
 526                                                         if (!phy_transaction_complete) begin
 527                                                                 if (user_command_mode) begin
 528                                                                         // Read the data byte to write from the active lane
 529                                                                         if (wishbone_sel[0]) begin
 530                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 531                                                                         end else if (wishbone_sel[1]) begin
 532                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 533                                                                         end else if (wishbone_sel[2]) begin
 534                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 535                                                                         end else if (wishbone_sel[3]) begin
 536                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 537                                                                         end else begin
 538                                                                                 phy_tx_data[7:0] = 8'hff;       // Safe default -- will not send any useful commands / data
 539                                                                         end
 540
 541                                                                         // Set up SPI access
 542                                                                         phy_tx_data[31:8] = 0;
 543                                                                         phy_qspi_mode_active <= 0;
 544                                                                         phy_qspi_transfer_mode <= 0;
 545                                                                         phy_dummy_cycle_count <= 0;
 546                                                                         phy_hold_ss_active <= 1;
 547                                                                         phy_cycle_start <= 1;
 548
 549                                                                         // Set user command mode active
 550                                                                         user_command_mode_active <= 1;
 551                                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC01;
 552                                                                 end else begin
 553                                                                         if (!wishbone_we) begin
 554                                                                                 // Set up SPI read access
 555                                                                                 if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 556                                                                                         if (four_byte_address_mode) begin
 557                                                                                                 if (fast_read_mode) begin
 558                                                                                                         phy_tx_data <= qspi_fast_read_4ba_command_code;
 559                                                                                                 end else begin
 560                                                                                                         phy_tx_data <= qspi_read_4ba_command_code;
 561                                                                                                 end
 562                                                                                         end else begin
 563                                                                                                 if (fast_read_mode) begin
 564                                                                                                         phy_tx_data <= qspi_fast_read_3ba_command_code;
 565                                                                                                 end else begin
 566                                                                                                         phy_tx_data <= qspi_read_3ba_command_code;
 567                                                                                                 end
 568                                                                                         end
 569                                                                                 end else begin
 570                                                                                         if (four_byte_address_mode) begin
 571                                                                                                 if (fast_read_mode) begin
 572                                                                                                         phy_tx_data <= spi_fast_read_4ba_command_code;
 573                                                                                                 end else begin
 574                                                                                                         phy_tx_data <= spi_read_4ba_command_code;
 575                                                                                                 end
 576                                                                                         end else begin
 577                                                                                                 if (fast_read_mode) begin
 578                                                                                                         phy_tx_data <= spi_fast_read_3ba_command_code;
 579                                                                                                 end else begin
 580                                                                                                         phy_tx_data <= spi_read_3ba_command_code;
 581                                                                                                 end
 582                                                                                         end
 583                                                                                 end
 584                                                                                 if (allow_multicycle_reads) begin
 585                                                                                         multicycle_read_in_progress <= 1;
 586                                                                                 end else begin
 587                                                                                         single_cycle_read_counter <= 0;
 588                                                                                 end
 589                                                                         end else begin
 590                                                                                 // Set up SPI write access
 591                                                                                 if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 592                                                                                         if (four_byte_address_mode) begin
 593                                                                                                 phy_tx_data <= qspi_program_4ba_command_code;
 594                                                                                         end else begin
 595                                                                                                 phy_tx_data <= qspi_program_3ba_command_code;
 596                                                                                         end
 597                                                                                 end else begin
 598                                                                                         if (four_byte_address_mode) begin
 599                                                                                                 phy_tx_data <= spi_program_4ba_command_code;
 600                                                                                         end else begin
 601                                                                                                 phy_tx_data <= spi_program_3ba_command_code;
 602                                                                                         end
 603                                                                                 end
 604                                                                                 if (allow_multicycle_writes) begin
 605                                                                                         multicycle_write_in_progress <= 1;
 606                                                                                 end else begin
 607                                                                                         single_cycle_write_counter <= 0;
 608                                                                                 end
 609                                                                         end
 610                                                                         phy_qspi_mode_active <= 0;
 611                                                                         phy_qspi_transfer_mode <= 0;
 612                                                                         phy_dummy_cycle_count <= 0;
 613                                                                         phy_hold_ss_active <= 1;
 614                                                                         phy_cycle_start <= 1;
 615
 616                                                                         if (four_byte_address_mode) begin
 617                                                                                 multicycle_transaction_address <= spi_address_reg;
 618                                                                         end else begin
 619                                                                                 multicycle_transaction_address <= {8'h00, spi_address_reg[23:0]};
 620                                                                         end
 621
 622                                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 623                                                                 end
 624                                                         end
 625                                                 end
 626                                         end
 627
 628                                         if ((spi_cs_active_hold_cycles > 0) && (multicycle_read_in_progress || multicycle_write_in_progress)) begin
 629                                                 spi_cs_active_counter <= spi_cs_active_counter + 1;
 630                                         end else begin
 631                                                 spi_cs_active_counter <= 0;
 632                                         end
 633                                 end
 634                                 SPI_MASTER_TRANSFER_STATE_UC01: begin
 635                                         if (phy_transaction_complete) begin
 636                                                 phy_cycle_start <= 0;
 637
 638                                                 user_command_mode_read_during_write <= phy_rx_data[7:0];
 639                                                 if (!wishbone_data_cycle_type) begin
 640                                                         // Read cycle
 641                                                         // Replicate the output bytes to all active lanes
 642                                                         if (wishbone_sel_reg[0]) begin
 643                                                                 wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 644                                                         end
 645                                                         if (wishbone_sel_reg[1]) begin
 646                                                                 wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 647                                                         end
 648                                                         if (wishbone_sel_reg[2]) begin
 649                                                                 wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 650                                                         end
 651                                                         if (wishbone_sel_reg[3]) begin
 652                                                                 wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 653                                                         end
 654                                                 end
 655
 656                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 657                                         end
 658                                 end
 659                                 SPI_MASTER_TRANSFER_STATE_UC02: begin
 660                                         // Release CS and prepare the SPI device for the next command
 661                                         phy_hold_ss_active <= 0;
 662                                         phy_qspi_transfer_mode <= 0;
 663                                         phy_qspi_mode_active <= 0;
 664
 665                                         // Terminate user command mode / multicycle transfers
 666                                         user_command_mode_active <= 0;
 667                                         multicycle_read_in_progress <= 0;
 668                                         multicycle_write_in_progress <= 0;
 669                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC03;
 670                                 end
 671                                 SPI_MASTER_TRANSFER_STATE_UC03: begin
 672                                         // Wait for CS to return to idle, since this state machine is running
 673                                         // significantly faster than the SPI PHY state machine.  This avoids
 674                                         // potentially short cycling the PHY and not allowing CS to return
 675                                         // to idle, thus inadvertently chaining the next command onto the
 676                                         // previous one!
 677                                         if (spi_ss_n) begin
 678                                                 if (cs_extra_idle_cycles > 0) begin
 679                                                         cs_extra_cycle_counter <= 1;
 680                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC04;
 681                                                 end else begin
 682                                                         // Return to idle
 683                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 684                                                 end
 685                                         end
 686                                 end
 687                                 SPI_MASTER_TRANSFER_STATE_UC04: begin
 688                                         if (cs_extra_cycle_counter >= cs_extra_idle_cycles) begin
 689                                                 // Return to idle
 690                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 691                                         end else begin
 692                                                 cs_extra_cycle_counter <= cs_extra_cycle_counter + 1;
 693                                         end
 694                                 end
 695                                 SPI_MASTER_TRANSFER_STATE_TR01: begin
 696                                         // Wait for CS to return to idle, since this state machine is running
 697                                         // significantly faster than the SPI PHY state machine.  This avoids
 698                                         // potentially short cycling the PHY and not allowing CS to return
 699                                         // to idle, thus inadvertently chaining the next command onto the
 700                                         // previous one!
 701                                         // If user command mode is active, CS will be asserted by design,
 702                                         // so ignore...
 703                                         if (spi_ss_n || user_command_mode_active
 704                                                 || multicycle_read_in_progress
 705                                                 || multicycle_write_in_progress) begin
 706                                                 if (!wishbone_data_cycle_type
 707                                                         && wishbone_access_is_32_bits
 708                                                         && !allow_multicycle_reads
 709                                                         && (single_cycle_read_counter < 4)) begin
 710                                                         // Set up SPI read access for next byte
 711                                                         if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 712                                                                 if (four_byte_address_mode) begin
 713                                                                         if (fast_read_mode) begin
 714                                                                                 phy_tx_data <= qspi_fast_read_4ba_command_code;
 715                                                                         end else begin
 716                                                                                 phy_tx_data <= qspi_read_4ba_command_code;
 717                                                                         end
 718                                                                 end else begin
 719                                                                         if (fast_read_mode) begin
 720                                                                                 phy_tx_data <= qspi_fast_read_3ba_command_code;
 721                                                                         end else begin
 722                                                                                 phy_tx_data <= qspi_read_3ba_command_code;
 723                                                                         end
 724                                                                 end
 725                                                         end else begin
 726                                                                 if (four_byte_address_mode) begin
 727                                                                         if (fast_read_mode) begin
 728                                                                                 phy_tx_data <= spi_fast_read_4ba_command_code;
 729                                                                         end else begin
 730                                                                                 phy_tx_data <= spi_read_4ba_command_code;
 731                                                                         end
 732                                                                 end else begin
 733                                                                         if (fast_read_mode) begin
 734                                                                                 phy_tx_data <= spi_fast_read_3ba_command_code;
 735                                                                         end else begin
 736                                                                                 phy_tx_data <= spi_read_3ba_command_code;
 737                                                                         end
 738                                                                 end
 739                                                         end
 740
 741                                                         phy_qspi_mode_active <= 0;
 742                                                         phy_qspi_transfer_mode <= 0;
 743                                                         phy_dummy_cycle_count <= 0;
 744                                                         phy_hold_ss_active <= 1;
 745                                                         phy_cycle_start <= 1;
 746
 747                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 748                                                 end else if (wishbone_data_cycle_type
 749                                                         && wishbone_access_is_32_bits
 750                                                         && !allow_multicycle_writes
 751                                                         && (single_cycle_write_counter < 4)) begin
 752                                                         // Set up SPI write access for next byte
 753                                                         if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 754                                                                 if (four_byte_address_mode) begin
 755                                                                         phy_tx_data <= qspi_program_4ba_command_code;
 756                                                                 end else begin
 757                                                                         phy_tx_data <= qspi_program_3ba_command_code;
 758                                                                 end
 759                                                         end else begin
 760                                                                 if (four_byte_address_mode) begin
 761                                                                         phy_tx_data <= spi_program_4ba_command_code;
 762                                                                 end else begin
 763                                                                         phy_tx_data <= spi_program_3ba_command_code;
 764                                                                 end
 765                                                         end
 766
 767                                                         phy_qspi_mode_active <= 0;
 768                                                         phy_qspi_transfer_mode <= 0;
 769                                                         phy_dummy_cycle_count <= 0;
 770                                                         phy_hold_ss_active <= 1;
 771                                                         phy_cycle_start <= 1;
 772
 773                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 774                                                 end else begin
 775                                                         // Signal transfer complete
 776                                                         wishbone_ack_reg <= 1;
 777
 778                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR02;
 779                                                 end
 780                                         end
 781                                 end
 782                                 SPI_MASTER_TRANSFER_STATE_TR02: begin
 783                                         // Cycle complete
 784                                         wishbone_ack_reg <= 0;
 785                                         spi_cs_active_counter <= 0;
 786                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 787                                 end
 788                                 SPI_MASTER_TRANSFER_STATE_TR03: begin
 789                                         if (phy_transaction_complete) begin
 790                                                 phy_cycle_start <= 0;
 791                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR04;
 792                                         end
 793                                 end
 794                                 SPI_MASTER_TRANSFER_STATE_TR04: begin
 795                                         if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 796                                                 if (!wishbone_data_cycle_type) begin
 797                                                         // Read
 798                                                         phy_qspi_mode_active <= qspi_read_quad_io_en;
 799                                                 end else begin
 800                                                         // Write
 801                                                         phy_qspi_mode_active <= qspi_write_quad_io_en;
 802                                                 end
 803                                         end else begin
 804                                                 phy_qspi_mode_active <= 0;
 805                                         end
 806                                         if (four_byte_address_mode) begin
 807                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR05;
 808                                         end else begin
 809                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR07;
 810                                         end
 811                                 end
 812                                 SPI_MASTER_TRANSFER_STATE_TR05: begin
 813                                         // Address (4 bytes / 1 word)
 814                                         if (!phy_transaction_complete) begin
 815                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
 816                                                         phy_tx_data <= multicycle_transaction_address;
 817                                                 end else begin
 818                                                         phy_tx_data <= spi_address_reg;
 819                                                 end
 820                                                 phy_qspi_transfer_mode <= 1;
 821                                                 phy_qspi_transfer_direction <= 1;
 822                                                 if (!wishbone_data_cycle_type) begin
 823                                                         // Read
 824                                                         if (fast_read_mode) begin
 825                                                                 phy_dummy_cycle_count <= dummy_cycle_count;
 826                                                         end else begin
 827                                                                 phy_dummy_cycle_count <= 0;
 828                                                         end
 829                                                 end else begin
 830                                                         // Write
 831                                                         phy_dummy_cycle_count <= 0;
 832                                                 end
 833                                                 phy_cycle_start <= 1;
 834
 835                                                 spi_byte_read_count <= 0;
 836                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR06;
 837                                         end
 838                                 end
 839                                 SPI_MASTER_TRANSFER_STATE_TR06: begin
 840                                         if (phy_transaction_complete) begin
 841                                                 phy_cycle_start <= 0;
 842
 843                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 844                                                         phy_qspi_mode_active <= 1;
 845                                                 end else begin
 846                                                         phy_qspi_mode_active <= 0;
 847                                                 end
 848
 849                                                 if (wishbone_data_cycle_type) begin
 850                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 851                                                 end else begin
 852                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 853                                                 end
 854                                         end
 855                                 end
 856                                 SPI_MASTER_TRANSFER_STATE_RD01: begin
 857                                         if (!phy_transaction_complete) begin
 858                                                 // Data words
 859                                                 phy_tx_data <= 0;       // Not used
 860                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 861                                                         phy_qspi_mode_active <= 1;
 862                                                 end else begin
 863                                                         phy_qspi_mode_active <= 0;
 864                                                 end
 865                                                 if (wishbone_access_is_32_bits && allow_multicycle_reads) begin
 866                                                         phy_qspi_transfer_mode <= 1;
 867                                                 end else begin
 868                                                         phy_qspi_transfer_mode <= 0;
 869                                                 end
 870                                                 phy_qspi_transfer_direction <= 0;
 871                                                 phy_dummy_cycle_count <= 0;
 872                                                 phy_cycle_start <= 1;
 873                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD02;
 874                                         end
 875                                 end
 876                                 SPI_MASTER_TRANSFER_STATE_RD02: begin
 877                                         if (phy_transaction_complete) begin
 878                                                 // Set Wishbone output data
 879                                                 if (wishbone_access_is_32_bits) begin
 880                                                         if (allow_multicycle_reads) begin
 881                                                                 wishbone_dat_r_reg <= phy_rx_data;
 882                                                                 multicycle_transaction_address <= multicycle_transaction_address + 4;
 883                                                         end else begin
 884                                                                 if (single_cycle_read_counter == 0) begin
 885                                                                         wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 886                                                                 end else if (single_cycle_read_counter == 1) begin
 887                                                                         wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 888                                                                 end else if (single_cycle_read_counter == 2) begin
 889                                                                         wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 890                                                                 end else if (single_cycle_read_counter == 3) begin
 891                                                                         wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 892                                                                 end
 893                                                                 single_cycle_read_counter <= single_cycle_read_counter + 1;
 894                                                                 multicycle_transaction_address <= multicycle_transaction_address + 1;
 895                                                         end
 896                                                 end else begin
 897                                                         // Replicate the data bytes to all active lanes
 898                                                         if (wishbone_sel_reg[0]) begin
 899                                                                 wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 900                                                         end
 901                                                         if (wishbone_sel_reg[1]) begin
 902                                                                 wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 903                                                         end
 904                                                         if (wishbone_sel_reg[2]) begin
 905                                                                 wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 906                                                         end
 907                                                         if (wishbone_sel_reg[3]) begin
 908                                                                 wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 909                                                         end
 910                                                         multicycle_transaction_address <= multicycle_transaction_address + 1;
 911                                                 end
 912
 913                                                 phy_cycle_start <= 0;
 914                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD03;
 915                                         end
 916                                 end
 917                                 SPI_MASTER_TRANSFER_STATE_RD03: begin
 918                                         if (!phy_transaction_complete) begin
 919                                                 // Release CS (if required)
 920                                                 if (!multicycle_read_in_progress) begin
 921                                                         phy_hold_ss_active <= 0;
 922                                                 end
 923
 924                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 925                                         end
 926                                 end
 927                                 SPI_MASTER_TRANSFER_STATE_WR01: begin
 928                                         if (!phy_transaction_complete) begin
 929                                                 // Data words
 930                                                 if (wishbone_access_is_32_bits) begin
 931                                                         if (allow_multicycle_writes) begin
 932                                                                 phy_tx_data <= wishbone_dat_w;
 933                                                                 phy_qspi_transfer_mode <= 1;
 934                                                                 multicycle_transaction_address <= multicycle_transaction_address + 4;
 935                                                         end else begin
 936                                                                 if (single_cycle_write_counter == 0) begin
 937                                                                         phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 938                                                                 end else if (single_cycle_write_counter == 1) begin
 939                                                                         phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 940                                                                 end else if (single_cycle_write_counter == 2) begin
 941                                                                         phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 942                                                                 end else if (single_cycle_write_counter == 3) begin
 943                                                                         phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 944                                                                 end
 945                                                                 phy_qspi_transfer_mode <= 0;
 946                                                                 single_cycle_write_counter <= single_cycle_write_counter + 1;
 947                                                                 multicycle_transaction_address <= multicycle_transaction_address + 1;
 948                                                         end
 949                                                 end else begin
 950                                                         // Write cycle
 951                                                         // Read the data byte to write from the active lane
 952                                                         if (wishbone_sel_reg[0]) begin
 953                                                                 phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 954                                                         end else if (wishbone_sel_reg[1]) begin
 955                                                                 phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 956                                                         end else if (wishbone_sel_reg[2]) begin
 957                                                                 phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 958                                                         end else if (wishbone_sel_reg[3]) begin
 959                                                                 phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 960                                                         end else begin
 961                                                                 phy_tx_data[7:0] = 8'hff;       // Safe default -- will not overwrite any bits
 962                                                         end
 963                                                         phy_tx_data[31:8] = 0;
 964                                                         phy_qspi_transfer_mode <= 0;
 965                                                         multicycle_transaction_address <= multicycle_transaction_address + 1;
 966                                                 end
 967                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 968                                                         phy_qspi_mode_active <= 1;
 969                                                 end else begin
 970                                                         phy_qspi_mode_active <= 0;
 971                                                 end
 972                                                 phy_qspi_transfer_direction <= 1;
 973                                                 phy_dummy_cycle_count <= 0;
 974                                                 phy_cycle_start <= 1;
 975                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR02;
 976                                         end
 977                                 end
 978                                 SPI_MASTER_TRANSFER_STATE_WR02: begin
 979                                         if (phy_transaction_complete) begin
 980                                                 phy_cycle_start <= 0;
 981
 982                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR03;
 983                                         end
 984                                 end
 985                                 SPI_MASTER_TRANSFER_STATE_WR03: begin
 986                                         if (!phy_transaction_complete) begin
 987                                                 // Release CS (if required)
 988                                                 if (!multicycle_write_in_progress) begin
 989                                                         phy_hold_ss_active <= 0;
 990                                                 end
 991
 992                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 993                                         end
 994                                 end
 995                                 SPI_MASTER_TRANSFER_STATE_TR07: begin
 996                                         // Send the three address bytes one at a time...
 997                                         if (!phy_transaction_complete) begin
 998                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
 999                                                         phy_tx_data <= multicycle_transaction_address[23:16];
1000                                                 end else begin
1001                                                         phy_tx_data <= spi_address_reg[23:16];
1002                                                 end
1003                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1004                                                         phy_qspi_mode_active <= 1;
1005                                                 end else begin
1006                                                         phy_qspi_mode_active <= 0;
1007                                                 end
1008                                                 phy_qspi_transfer_mode <= 0;
1009                                                 phy_qspi_transfer_direction <= 1;
1010                                                 phy_dummy_cycle_count <= 0;
1011                                                 phy_cycle_start <= 1;
1012
1013                                                 spi_byte_read_count <= 0;
1014                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR08;
1015                                         end
1016                                 end
1017                                 SPI_MASTER_TRANSFER_STATE_TR08: begin
1018                                         if (phy_transaction_complete) begin
1019                                                 phy_cycle_start <= 0;
1020                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR09;
1021                                         end
1022                                 end
1023                                 SPI_MASTER_TRANSFER_STATE_TR09: begin
1024                                         if (!phy_transaction_complete) begin
1025                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1026                                                         phy_tx_data <= multicycle_transaction_address[15:8];
1027                                                 end else begin
1028                                                         phy_tx_data <= spi_address_reg[15:8];
1029                                                 end
1030                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1031                                                         phy_qspi_mode_active <= 1;
1032                                                 end else begin
1033                                                         phy_qspi_mode_active <= 0;
1034                                                 end
1035                                                 phy_qspi_transfer_mode <= 0;
1036                                                 phy_qspi_transfer_direction <= 1;
1037                                                 phy_dummy_cycle_count <= 0;
1038                                                 phy_cycle_start <= 1;
1039
1040                                                 spi_byte_read_count <= 0;
1041                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR10;
1042                                         end
1043                                 end
1044                                 SPI_MASTER_TRANSFER_STATE_TR10: begin
1045                                         if (phy_transaction_complete) begin
1046                                                 phy_cycle_start <= 0;
1047                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR11;
1048                                         end
1049                                 end
1050                                 SPI_MASTER_TRANSFER_STATE_TR11: begin
1051                                         if (!phy_transaction_complete) begin
1052                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1053                                                         phy_tx_data <= multicycle_transaction_address[7:0];
1054                                                 end else begin
1055                                                         phy_tx_data <= spi_address_reg[7:0];
1056                                                 end
1057                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1058                                                         phy_qspi_mode_active <= 1;
1059                                                 end else begin
1060                                                         phy_qspi_mode_active <= 0;
1061                                                 end
1062                                                 phy_qspi_transfer_mode <= 0;
1063                                                 phy_qspi_transfer_direction <= 1;
1064                                                 if (!wishbone_data_cycle_type) begin
1065                                                         // Read
1066                                                         if (fast_read_mode) begin
1067                                                                 phy_dummy_cycle_count <= dummy_cycle_count;
1068                                                         end else begin
1069                                                                 phy_dummy_cycle_count <= 0;
1070                                                         end
1071                                                 end else begin
1072                                                         phy_dummy_cycle_count <= 0;
1073                                                 end
1074                                                 phy_cycle_start <= 1;
1075
1076                                                 spi_byte_read_count <= 0;
1077                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR12;
1078                                         end
1079                                 end
1080                                 SPI_MASTER_TRANSFER_STATE_TR12: begin
1081                                         if (phy_transaction_complete) begin
1082                                                 phy_cycle_start <= 0;
1083                                                 if (wishbone_data_cycle_type) begin
1084                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
1085                                                 end else begin
1086                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
1087                                                 end
1088                                         end
1089                                 end
1090                                 default: begin
1091                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
1092                                 end
1093                         endcase
1094                 end
1095         end
1096 endmodule