test/test_emif.py

   1 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 import unittest
   5
   6 from migen import *
   7
   8 from litex.soc.interconnect import wishbone
   9
  10 from litex.soc.cores.emif import EMIF
  11
  12
  13 class EMIFPads:
  14     def __init__(self):
  15         self.cs_n   = Signal(reset=1)
  16         self.we_n   = Signal(reset=1)
  17         self.oe_n   = Signal(reset=1)
  18         self.wait_n = Signal(reset=1)
  19         self.ba     = Signal(2)
  20         self.addr   = Signal(22)
  21         self.dqm_n  = Signal(2)
  22         self.data   = Record([("oe", 1), ("o", 16), ("i", 16)])
  23
  24
  25 def emif_write(pads, addr, data, release_cs=True):
  26     for i in range(2):
  27         yield pads.cs_n.eq(0)
  28         yield pads.we_n.eq(1)
  29         yield pads.oe_n.eq(1)
  30         yield pads.ba.eq(1<<i)
  31         yield pads.addr.eq(addr)
  32         yield pads.data.i.eq((data >> 16*i) & 0xffff)
  33         yield
  34         yield pads.we_n.eq(0)
  35         for i in range(8):
  36             yield
  37         yield pads.we_n.eq(1)
  38         yield
  39         yield pads.cs_n.eq(release_cs)
  40         yield
  41
  42
  43 def emif_read(pads, addr, release_cs=True, release_oe=True):
  44     data = 0
  45     for i in range(2):
  46         yield pads.cs_n.eq(0)
  47         yield pads.we_n.eq(1)
  48         yield pads.oe_n.eq(release_oe)
  49         yield pads.ba.eq(1<<i)
  50         yield pads.addr.eq(addr)
  51         yield
  52         yield pads.oe_n.eq(0)
  53         for i in range(8):
  54             yield
  55         data >>= 16
  56         data |= (yield pads.data.o) << 16
  57         yield pads.oe_n.eq(release_oe)
  58         yield
  59         yield pads.cs_n.eq(release_cs)
  60         yield
  61     return data
  62
  63
  64 class TestEMIF(unittest.TestCase):
  65     def test_emif(self):
  66         pads = EMIFPads()
  67         def generator(dut):
  68             # Test writes/reads with cs release between accesses
  69             yield from emif_write(pads, 0, 0xdeadbeef, True)
  70             yield from emif_write(pads, 1, 0x12345678, True)
  71             yield from emif_write(pads, 2, 0x5aa55aa5, True)
  72             self.assertEqual((yield from emif_read(pads, 0, True)), 0xdeadbeef)
  73             self.assertEqual((yield from emif_read(pads, 1, True)), 0x12345678)
  74             self.assertEqual((yield from emif_read(pads, 2, True)), 0x5aa55aa5)
  75
  76             # Test writes/reads without cs release between accesses
  77             yield from emif_write(pads, 0, 0xdeadbeef, False)
  78             yield from emif_write(pads, 1, 0x12345678, False)
  79             yield from emif_write(pads, 2, 0x5aa55aa5, False)
  80             self.assertEqual((yield from emif_read(pads, 0, False)), 0xdeadbeef)
  81             self.assertEqual((yield from emif_read(pads, 1, False)), 0x12345678)
  82             self.assertEqual((yield from emif_read(pads, 2, False)), 0x5aa55aa5)
  83
  84         class DUT(Module):
  85             def __init__(self, pads):
  86                 emif = EMIF(pads)
  87                 self.submodules += emif
  88                 mem = wishbone.SRAM(16, bus=emif.bus)
  89                 self.submodules += mem
  90         dut = DUT(pads)
  91         run_simulation(dut, [generator(dut)])