soc/integration/csr_bridge: use registered version only when SDRAM is present.
[litex.git] / test / test_icap.py
1 # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
2 # License: BSD
3
4 import unittest
5
6 from migen import *
7
8 from litex.soc.cores.icap import ICAP, ICAPBitstream
9
10
11 class TestICAP(unittest.TestCase):
12 def test_icap_command_reload(self):
13 def generator(dut):
14 yield dut.addr.storage.eq(0x4)
15 yield dut.data.storage.eq(0xf)
16 for i in range(16):
17 yield
18 yield dut.send.re.eq(1)
19 yield
20 yield dut.send.re.eq(0)
21 for i in range(256):
22 yield
23
24 dut = ICAP(simulation=True)
25 clocks = {"sys": 10,
26 "icap":20}
27 run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd")
28
29 def test_icap_bitstream_syntax(self):
30 dut = ICAPBitstream(simulation=True)