test/test_targets.py

   1 # This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # This file is Copyright (c) 2019 Tim 'mithro' Ansell <me@mith.ro>
   3 # License: BSD
   4
   5 import subprocess
   6 import unittest
   7 import os
   8
   9 from migen import *
  10
  11 from litex.soc.integration.builder import *
  12
  13
  14 RUNNING_ON_TRAVIS = (os.getenv('TRAVIS', 'false').lower() == 'true')
  15
  16
  17 def build_test(socs):
  18     errors = 0
  19     for soc in socs:
  20         os.system("rm -rf build")
  21         builder = Builder(soc, compile_software=False, compile_gateware=False)
  22         builder.build()
  23         errors += not os.path.isfile("build/{build_name}/gateware/{build_name}.v".format(build_name=soc.build_name))
  24     os.system("rm -rf build")
  25     return errors
  26
  27 test_kwargs = {
  28     "integrated_rom_size": 0x8000,
  29     "max_sdram_size": 0x4000000
  30 }
  31
  32 class TestTargets(unittest.TestCase):
  33     # Altera boards
  34     def test_de0nano(self):
  35         from litex.boards.targets.de0nano import BaseSoC
  36         errors = build_test([BaseSoC(**test_kwargs)])
  37         self.assertEqual(errors, 0)
  38
  39     # Xilinx boards
  40     # Spartan-6
  41     def test_minispartan6(self):
  42         from litex.boards.targets.minispartan6 import BaseSoC
  43         errors = build_test([BaseSoC(**test_kwargs)])
  44         self.assertEqual(errors, 0)
  45
  46     # Artix-7
  47     def test_arty(self):
  48         from litex.boards.targets.arty import BaseSoC
  49         errors = build_test([
  50             BaseSoC(**test_kwargs),
  51             BaseSoC(with_ethernet=True, **test_kwargs)
  52         ])
  53         self.assertEqual(errors, 0)
  54
  55     def test_netv2(self):
  56         from litex.boards.targets.netv2 import BaseSoC
  57         errors = build_test([
  58             BaseSoC(**test_kwargs),
  59             BaseSoC(with_ethernet=True, **test_kwargs)
  60         ])
  61         self.assertEqual(errors, 0)
  62
  63     def test_nexys4ddr(self):
  64         from litex.boards.targets.nexys4ddr import BaseSoC
  65         errors = build_test([BaseSoC(**test_kwargs)])
  66         self.assertEqual(errors, 0)
  67
  68     def test_nexys_video(self):
  69         from litex.boards.targets.nexys_video import BaseSoC
  70         errors = build_test([
  71             BaseSoC(**test_kwargs),
  72             BaseSoC(with_ethernet=True, **test_kwargs)
  73         ])
  74         self.assertEqual(errors, 0)
  75
  76     def test_arty_symbiflow(self):
  77         from litex.boards.targets.arty import BaseSoC
  78         errors = build_test([
  79             BaseSoC(toolchain="symbiflow", **test_kwargs)
  80         ])
  81         self.assertEqual(errors, 0)
  82
  83     # Kintex-7
  84     def test_genesys2(self):
  85         from litex.boards.targets.genesys2 import BaseSoC
  86         errors = build_test([
  87             BaseSoC(**test_kwargs),
  88             BaseSoC(with_ethernet=True, **test_kwargs)
  89         ])
  90         self.assertEqual(errors, 0)
  91
  92     def test_kc705(self):
  93         from litex.boards.targets.kc705 import BaseSoC
  94         errors = build_test([
  95             BaseSoC(**test_kwargs),
  96             BaseSoC(with_ethernet=True, **test_kwargs)
  97         ])
  98         self.assertEqual(errors, 0)
  99
 100     # Kintex-Ultrascale
 101     def test_kcu105(self):
 102         from litex.boards.targets.kcu105 import BaseSoC
 103         errors = build_test([BaseSoC(**test_kwargs)])
 104         self.assertEqual(errors, 0)
 105
 106     # Lattice boards
 107     # ECP5
 108     def test_versa_ecp5(self):
 109         from litex.boards.targets.versa_ecp5 import BaseSoC
 110         errors = build_test([BaseSoC(**test_kwargs)])
 111         self.assertEqual(errors, 0)
 112
 113     def test_ulx3s(self):
 114         from litex.boards.targets.ulx3s import BaseSoC
 115         errors = build_test([BaseSoC(**test_kwargs)])
 116         self.assertEqual(errors, 0)
 117
 118     # Build simple design for all platforms
 119     def test_simple(self):
 120         platforms = []
 121         # Xilinx
 122         platforms += ["minispartan6"]                              # Spartan6
 123         platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7
 124         platforms += ["kc705", "genesys2"]                         # Kintex7
 125         platforms += ["kcu105"]                                    # Kintex Ultrascale
 126
 127         # Altera/Intel
 128         platforms += ["de0nano"]                                   # Cyclone4
 129
 130         # Lattice
 131         platforms += ["tinyfpga_bx"]                               # iCE40
 132         platforms += ["machxo3"]                                   # MachXO3
 133         platforms += ["versa_ecp5", "ulx3s"]                       # ECP5
 134
 135         # Microsemi
 136         platforms += ["avalanche"]                                 # PolarFire
 137
 138         for p in platforms:
 139             with self.subTest(platform=p):
 140                 cmd = """\
 141 litex/boards/targets/simple.py litex.boards.platforms.{p} \
 142     --cpu-type=vexriscv     \
 143     --no-compile-software   \
 144     --uart-name=stub        \
 145 """.format(p=p)
 146                 subprocess.check_call(cmd, shell=True)
 147
 148     def test_z_cpu_none(self): # FIXME: workaround to execute it last.
 149         from litex.boards.targets.arty import BaseSoC
 150         errors = build_test([BaseSoC(cpu_type=None)])
 151         self.assertEqual(errors, 0)
 152
 153     def run_variants(self, cpu, variants):
 154         for v in variants:
 155             with self.subTest(cpu=cpu, variant=v):
 156                 self.run_variant(cpu, v)
 157
 158     def run_variant(self, cpu, variant):
 159         cmd = """\
 160 litex/boards/targets/simple.py litex.boards.platforms.arty \
 161     --cpu-type={c}          \
 162     --cpu-variant={v}       \
 163     --no-compile-software   \
 164     --uart-name=stub        \
 165 """.format(c=cpu, v=variant)
 166         subprocess.check_output(cmd, shell=True)
 167
 168     # Build some variants for the arty platform to make sure they work.
 169     def test_variants_picorv32(self):
 170         self.run_variants("picorv32", ('standard', 'minimal'))
 171
 172     def test_variants_vexriscv(self):
 173         self.run_variants("vexriscv", ('standard', 'minimal', 'lite', 'lite+debug', 'full+debug'))
 174
 175     @unittest.skipIf(RUNNING_ON_TRAVIS, "No nMigen/Yosys on Travis-CI")
 176     def test_variants_minerva(self):
 177         self.run_variants("minerva", ('standard',))
 178
 179     def test_variants_vexriscv(self):
 180         cpu_variants = {
 181             'vexriscv': ('standard', 'minimal', 'lite', 'lite+debug', 'full+debug'),
 182         }
 183         for cpu, variants in cpu_variants.items():
 184             self.run_variants(cpu, variants)
 185
 186     @unittest.skipIf(RUNNING_ON_TRAVIS, "No lm32 toolchain on Travis-CI")
 187     def test_variants_lm32(self):
 188         self.run_variants('lm32', ('standard', 'minimal', 'lite'))
 189
 190     @unittest.skipIf(RUNNING_ON_TRAVIS, "No or1k toolchain on Travis-CI")
 191     def test_variants_mor1kx(self):
 192         self.run_variants('mor1kx', ('standard', 'linux'))