tests/cover.sv

   1 module top (
   2         input clk,
   3         input [7:0] din
   4 );
   5         reg [31:0] state = 0;
   6
   7         always @(posedge clk) begin
   8                 state <= ((state << 5) + state) ^ din;
   9         end
  10
  11 `ifdef FORMAL
  12         always @(posedge clk) begin
  13                 cover (state == 'd 12345678);
  14                 cover (state == 'h 12345678);
  15         end
  16 `endif
  17 endmodule