tests/keepgoing_multi_step.sv

   1 module test (
   2         input clk, a
   3 );
   4         reg [7:0] counter = 0;
   5
   6         always @(posedge clk) begin
   7                 counter <= counter + 1;
   8         end
   9
  10         always @(posedge clk) begin
  11                 assert(0);
  12                 if (counter == 3 || counter == 7) begin
  13                         assert(a); // step 3,7
  14                 end
  15                 if (counter == 5) begin
  16                         assert(a); // step 5
  17                 end
  18                 if (counter == 7) begin
  19                         assert(a); // step 7
  20                 end
  21         end
  22 endmodule