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verific: Improve logic generated for SVA value change expressions
[yosys.git] / tests / sva / .gitignore
1 /*_pass.sby
2 /*_fail.sby
3 /*_pass
4 /*_fail
5 /*.ok
6 /*.fst
7 /vhdlpsl[0-9][0-9]
8 /vhdlpsl[0-9][0-9].sby