tests/test_build_dsl.py

   1 from collections import OrderedDict
   2
   3 from nmigen.build.dsl import *
   4
   5 from .utils import *
   6
   7
   8 class PinsTestCase(FHDLTestCase):
   9     def test_basic(self):
  10         p = Pins("A0 A1 A2")
  11         self.assertEqual(repr(p), "(pins io A0 A1 A2)")
  12         self.assertEqual(len(p.names), 3)
  13         self.assertEqual(p.dir, "io")
  14         self.assertEqual(p.invert, False)
  15         self.assertEqual(list(p), ["A0", "A1", "A2"])
  16
  17     def test_invert(self):
  18         p = PinsN("A0")
  19         self.assertEqual(repr(p), "(pins-n io A0)")
  20         self.assertEqual(p.invert, True)
  21
  22     def test_invert_arg(self):
  23         p = Pins("A0", invert=True)
  24         self.assertEqual(p.invert, True)
  25
  26     def test_conn(self):
  27         p = Pins("0 1 2", conn=("pmod", 0))
  28         self.assertEqual(list(p), ["pmod_0:0", "pmod_0:1", "pmod_0:2"])
  29         p = Pins("0 1 2", conn=("pmod", "a"))
  30         self.assertEqual(list(p), ["pmod_a:0", "pmod_a:1", "pmod_a:2"])
  31
  32     def test_map_names(self):
  33         p = Pins("0 1 2", conn=("pmod", 0))
  34         mapping = {
  35             "pmod_0:0": "A0",
  36             "pmod_0:1": "A1",
  37             "pmod_0:2": "A2",
  38         }
  39         self.assertEqual(p.map_names(mapping, p), ["A0", "A1", "A2"])
  40
  41     def test_map_names_recur(self):
  42         p = Pins("0", conn=("pmod", 0))
  43         mapping = {
  44             "pmod_0:0": "ext_0:1",
  45             "ext_0:1":  "A1",
  46         }
  47         self.assertEqual(p.map_names(mapping, p), ["A1"])
  48
  49     def test_wrong_names(self):
  50         with self.assertRaisesRegex(TypeError,
  51                 r"^Names must be a whitespace-separated string, not \['A0', 'A1', 'A2'\]$"):
  52             p = Pins(["A0", "A1", "A2"])
  53
  54     def test_wrong_dir(self):
  55         with self.assertRaisesRegex(TypeError,
  56                 r"^Direction must be one of \"i\", \"o\", \"oe\", or \"io\", not 'wrong'$"):
  57             p = Pins("A0 A1", dir="wrong")
  58
  59     def test_wrong_conn(self):
  60         with self.assertRaisesRegex(TypeError,
  61                 (r"^Connector must be None or a pair of string \(connector name\) and "
  62                     r"integer\/string \(connector number\), not \('foo', None\)$")):
  63             p = Pins("A0 A1", conn=("foo", None))
  64
  65     def test_wrong_map_names(self):
  66         p = Pins("0 1 2", conn=("pmod", 0))
  67         mapping = {
  68             "pmod_0:0": "A0",
  69         }
  70         with self.assertRaisesRegex(NameError,
  71                 (r"^Resource \(pins io pmod_0:0 pmod_0:1 pmod_0:2\) refers to nonexistent "
  72                     r"connector pin pmod_0:1$")):
  73             p.map_names(mapping, p)
  74
  75     def test_wrong_assert_width(self):
  76         with self.assertRaisesRegex(AssertionError,
  77                 r"^3 names are specified \(0 1 2\), but 4 names are expected$"):
  78             Pins("0 1 2", assert_width=4)
  79
  80
  81 class DiffPairsTestCase(FHDLTestCase):
  82     def test_basic(self):
  83         dp = DiffPairs(p="A0 A1", n="B0 B1")
  84         self.assertEqual(repr(dp), "(diffpairs io (p A0 A1) (n B0 B1))")
  85         self.assertEqual(dp.p.names, ["A0", "A1"])
  86         self.assertEqual(dp.n.names, ["B0", "B1"])
  87         self.assertEqual(dp.dir, "io")
  88         self.assertEqual(list(dp), [("A0", "B0"), ("A1", "B1")])
  89
  90     def test_invert(self):
  91         dp = DiffPairsN(p="A0", n="B0")
  92         self.assertEqual(repr(dp), "(diffpairs-n io (p A0) (n B0))")
  93         self.assertEqual(dp.p.names, ["A0"])
  94         self.assertEqual(dp.n.names, ["B0"])
  95         self.assertEqual(dp.invert, True)
  96
  97     def test_conn(self):
  98         dp = DiffPairs(p="0 1 2", n="3 4 5", conn=("pmod", 0))
  99         self.assertEqual(list(dp), [
 100             ("pmod_0:0", "pmod_0:3"),
 101             ("pmod_0:1", "pmod_0:4"),
 102             ("pmod_0:2", "pmod_0:5"),
 103         ])
 104
 105     def test_dir(self):
 106         dp = DiffPairs("A0", "B0", dir="o")
 107         self.assertEqual(dp.dir, "o")
 108         self.assertEqual(dp.p.dir, "o")
 109         self.assertEqual(dp.n.dir, "o")
 110
 111     def test_wrong_width(self):
 112         with self.assertRaisesRegex(TypeError,
 113                 (r"^Positive and negative pins must have the same width, but \(pins io A0\) "
 114                     r"and \(pins io B0 B1\) do not$")):
 115             dp = DiffPairs("A0", "B0 B1")
 116
 117     def test_wrong_assert_width(self):
 118         with self.assertRaisesRegex(AssertionError,
 119                 r"^3 names are specified \(0 1 2\), but 4 names are expected$"):
 120             DiffPairs("0 1 2", "3 4 5", assert_width=4)
 121
 122
 123 class AttrsTestCase(FHDLTestCase):
 124     def test_basic(self):
 125         a = Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)
 126         self.assertEqual(a["IO_STANDARD"], "LVCMOS33")
 127         self.assertEqual(repr(a), "(attrs IO_STANDARD='LVCMOS33' PULLUP=1)")
 128
 129     def test_remove(self):
 130         a = Attrs(FOO=None)
 131         self.assertEqual(a["FOO"], None)
 132         self.assertEqual(repr(a), "(attrs !FOO)")
 133
 134     def test_callable(self):
 135         fn = lambda self: "FOO"
 136         a = Attrs(FOO=fn)
 137         self.assertEqual(a["FOO"], fn)
 138         self.assertEqual(repr(a), "(attrs FOO={!r})".format(fn))
 139
 140     def test_wrong_value(self):
 141         with self.assertRaisesRegex(TypeError,
 142                 r"^Value of attribute FOO must be None, int, str, or callable, not 1\.0$"):
 143             a = Attrs(FOO=1.0)
 144
 145
 146 class ClockTestCase(FHDLTestCase):
 147     def test_basic(self):
 148         c = Clock(1_000_000)
 149         self.assertEqual(c.frequency, 1e6)
 150         self.assertEqual(c.period, 1e-6)
 151         self.assertEqual(repr(c), "(clock 1000000.0)")
 152
 153
 154 class SubsignalTestCase(FHDLTestCase):
 155     def test_basic_pins(self):
 156         s = Subsignal("a", Pins("A0"), Attrs(IOSTANDARD="LVCMOS33"))
 157         self.assertEqual(repr(s),
 158             "(subsignal a (pins io A0) (attrs IOSTANDARD='LVCMOS33'))")
 159
 160     def test_basic_diffpairs(self):
 161         s = Subsignal("a", DiffPairs("A0", "B0"))
 162         self.assertEqual(repr(s),
 163             "(subsignal a (diffpairs io (p A0) (n B0)))")
 164
 165     def test_basic_subsignals(self):
 166         s = Subsignal("a",
 167                 Subsignal("b", Pins("A0")),
 168                 Subsignal("c", Pins("A1")))
 169         self.assertEqual(repr(s),
 170             "(subsignal a (subsignal b (pins io A0)) "
 171                          "(subsignal c (pins io A1)))")
 172
 173     def test_attrs(self):
 174         s = Subsignal("a",
 175                 Subsignal("b", Pins("A0")),
 176                 Subsignal("c", Pins("A0"), Attrs(SLEW="FAST")),
 177                 Attrs(IOSTANDARD="LVCMOS33"))
 178         self.assertEqual(s.attrs, {"IOSTANDARD": "LVCMOS33"})
 179         self.assertEqual(s.ios[0].attrs, {})
 180         self.assertEqual(s.ios[1].attrs, {"SLEW": "FAST"})
 181
 182     def test_attrs_many(self):
 183         s = Subsignal("a", Pins("A0"), Attrs(SLEW="FAST"), Attrs(PULLUP="1"))
 184         self.assertEqual(s.attrs, {"SLEW": "FAST", "PULLUP": "1"})
 185
 186     def test_clock(self):
 187         s = Subsignal("a", Pins("A0"), Clock(1e6))
 188         self.assertEqual(s.clock.frequency, 1e6)
 189
 190     def test_wrong_empty_io(self):
 191         with self.assertRaisesRegex(ValueError, r"^Missing I\/O constraints$"):
 192             s = Subsignal("a")
 193
 194     def test_wrong_io(self):
 195         with self.assertRaisesRegex(TypeError,
 196                 (r"^Constraint must be one of Pins, DiffPairs, Subsignal, Attrs, or Clock, "
 197                     r"not 'wrong'$")):
 198             s = Subsignal("a", "wrong")
 199
 200     def test_wrong_pins(self):
 201         with self.assertRaisesRegex(TypeError,
 202                 (r"^Pins and DiffPairs are incompatible with other location or subsignal "
 203                     r"constraints, but \(pins io A1\) appears after \(pins io A0\)$")):
 204             s = Subsignal("a", Pins("A0"), Pins("A1"))
 205
 206     def test_wrong_diffpairs(self):
 207         with self.assertRaisesRegex(TypeError,
 208                 (r"^Pins and DiffPairs are incompatible with other location or subsignal "
 209                     r"constraints, but \(pins io A1\) appears after \(diffpairs io \(p A0\) \(n B0\)\)$")):
 210             s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1"))
 211
 212     def test_wrong_subsignals(self):
 213         with self.assertRaisesRegex(TypeError,
 214                 (r"^Pins and DiffPairs are incompatible with other location or subsignal "
 215                     r"constraints, but \(pins io B0\) appears after \(subsignal b \(pins io A0\)\)$")):
 216             s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0"))
 217
 218     def test_wrong_clock(self):
 219         with self.assertRaisesRegex(TypeError,
 220                 (r"^Clock constraint can only be applied to Pins or DiffPairs, not "
 221                     r"\(subsignal b \(pins io A0\)\)$")):
 222             s = Subsignal("a", Subsignal("b", Pins("A0")), Clock(1e6))
 223
 224     def test_wrong_clock_many(self):
 225         with self.assertRaisesRegex(ValueError,
 226                 r"^Clock constraint can be applied only once$"):
 227             s = Subsignal("a", Pins("A0"), Clock(1e6), Clock(1e7))
 228
 229
 230 class ResourceTestCase(FHDLTestCase):
 231     def test_basic(self):
 232         r = Resource("serial", 0,
 233                 Subsignal("tx", Pins("A0", dir="o")),
 234                 Subsignal("rx", Pins("A1", dir="i")),
 235                 Attrs(IOSTANDARD="LVCMOS33"))
 236         self.assertEqual(repr(r), "(resource serial 0"
 237                                   " (subsignal tx (pins o A0))"
 238                                   " (subsignal rx (pins i A1))"
 239                                   " (attrs IOSTANDARD='LVCMOS33'))")
 240
 241     def test_family(self):
 242         ios = [Subsignal("clk", Pins("A0", dir="o"))]
 243         r1  = Resource.family(0, default_name="spi", ios=ios)
 244         r2  = Resource.family("spi_flash", 0, default_name="spi", ios=ios)
 245         r3  = Resource.family("spi_flash", 0, default_name="spi", ios=ios, name_suffix="4x")
 246         r4  = Resource.family(0, default_name="spi", ios=ios, name_suffix="2x")
 247         self.assertEqual(r1.name, "spi")
 248         self.assertEqual(r1.ios, ios)
 249         self.assertEqual(r2.name, "spi_flash")
 250         self.assertEqual(r2.ios, ios)
 251         self.assertEqual(r3.name, "spi_flash_4x")
 252         self.assertEqual(r3.ios, ios)
 253         self.assertEqual(r4.name, "spi_2x")
 254         self.assertEqual(r4.ios, ios)
 255
 256
 257 class ConnectorTestCase(FHDLTestCase):
 258     def test_string(self):
 259         c = Connector("pmod", 0, "A0 A1 A2 A3 - - A4 A5 A6 A7 - -")
 260         self.assertEqual(c.name, "pmod")
 261         self.assertEqual(c.number, 0)
 262         self.assertEqual(c.mapping, OrderedDict([
 263             ("1", "A0"),
 264             ("2", "A1"),
 265             ("3", "A2"),
 266             ("4", "A3"),
 267             ("7", "A4"),
 268             ("8", "A5"),
 269             ("9", "A6"),
 270             ("10", "A7"),
 271         ]))
 272         self.assertEqual(list(c), [
 273             ("pmod_0:1", "A0"),
 274             ("pmod_0:2", "A1"),
 275             ("pmod_0:3", "A2"),
 276             ("pmod_0:4", "A3"),
 277             ("pmod_0:7", "A4"),
 278             ("pmod_0:8", "A5"),
 279             ("pmod_0:9", "A6"),
 280             ("pmod_0:10", "A7"),
 281         ])
 282         self.assertEqual(repr(c),
 283             "(connector pmod 0 1=>A0 2=>A1 3=>A2 4=>A3 7=>A4 8=>A5 9=>A6 10=>A7)")
 284
 285     def test_dict(self):
 286         c = Connector("ext", 1, {"DP0": "A0", "DP1": "A1"})
 287         self.assertEqual(c.name, "ext")
 288         self.assertEqual(c.number, 1)
 289         self.assertEqual(c.mapping, OrderedDict([
 290             ("DP0", "A0"),
 291             ("DP1", "A1"),
 292         ]))
 293
 294     def test_conn(self):
 295         c = Connector("pmod", 0, "0 1 2 3 - - 4 5 6 7 - -", conn=("expansion", 0))
 296         self.assertEqual(c.mapping, OrderedDict([
 297             ("1", "expansion_0:0"),
 298             ("2", "expansion_0:1"),
 299             ("3", "expansion_0:2"),
 300             ("4", "expansion_0:3"),
 301             ("7", "expansion_0:4"),
 302             ("8", "expansion_0:5"),
 303             ("9", "expansion_0:6"),
 304             ("10", "expansion_0:7"),
 305         ]))
 306
 307     def test_str_name(self):
 308         c = Connector("ext", "A", "0 1 2")
 309         self.assertEqual(c.name, "ext")
 310         self.assertEqual(c.number, "A")
 311
 312     def test_conn_wrong_name(self):
 313         with self.assertRaisesRegex(TypeError,
 314                 (r"^Connector must be None or a pair of string \(connector name\) and "
 315                     r"integer\/string \(connector number\), not \('foo', None\)$")):
 316             Connector("ext", "A", "0 1 2", conn=("foo", None))
 317
 318     def test_wrong_io(self):
 319         with self.assertRaisesRegex(TypeError,
 320                 r"^Connector I\/Os must be a dictionary or a string, not \[\]$"):
 321             Connector("pmod", 0, [])
 322
 323     def test_wrong_dict_key_value(self):
 324         with self.assertRaisesRegex(TypeError,
 325                 r"^Connector pin name must be a string, not 0$"):
 326             Connector("pmod", 0, {0: "A"})
 327         with self.assertRaisesRegex(TypeError,
 328                 r"^Platform pin name must be a string, not 0$"):
 329             Connector("pmod", 0, {"A": 0})