tests/verilog/always_comb_nolatch_5.ys

   1 read_verilog -sv <<EOF
   2 module top;
   3 logic [4:0] x;
   4 logic z;
   5 assign z = 1'b1;
   6 always_comb begin : foo
   7     x = '0;
   8     if (z) begin : bar
   9         for (int i = 0; i < 5; i++)
  10             x[i] = 1'b1;
  11     end
  12 end
  13 endmodule
  14 EOF
  15 proc