unused_please_ignore_completely/experiment/l0_cache.py

   1 class DualPortSplitter(Elaboratable):
   2     """DualPortSplitter
   3
   4     * one incoming PortInterface
   5     * two *OUTGOING* PortInterfaces
   6     * uses LDSTSplitter to do it
   7
   8     (actually, thinking about it LDSTSplitter could simply be
   9      modified to conform to PortInterface: one in, two out)
  10
  11     once that is done each pair of ports may be wired directly
  12     to the dual ports of L0CacheBuffer
  13
  14     The split is carried out so that, regardless of alignment or
  15     mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
  16     of the address, whilst outgoing PortInterface[1] takes
  17     bit 4 == 1.
  18
  19     PortInterface *may* need to be changed so that the length is
  20     a binary number (accepting values 1-16).
  21     """
  22
  23     def __init__(self,inp):
  24         self.outp = [PortInterface(name="outp_0"),
  25                      PortInterface(name="outp_1")]
  26         print(self.outp)
  27
  28     def elaborate(self, platform):
  29         m = Module()
  30         comb = m.d.comb
  31         m.submodules.splitter = splitter = LDSTSplitter(64, 48, 4)
  32         self.inp = splitter.pi
  33         comb += splitter.addr_i.eq(self.inp.addr)  # XXX
  34         #comb += splitter.len_i.eq()
  35         #comb += splitter.valid_i.eq()
  36         comb += splitter.is_ld_i.eq(self.inp.is_ld_i)
  37         comb += splitter.is_st_i.eq(self.inp.is_st_i)
  38         #comb += splitter.st_data_i.eq()
  39         #comb += splitter.sld_valid_i.eq()
  40         #comb += splitter.sld_data_i.eq()
  41         #comb += splitter.sst_valid_i.eq()
  42         return m