versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5 import sys
   6
   7 import litex_boards.targets.versa_ecp5 as versa_ecp5
   8 import litex_boards.targets.ulx3s as ulx3s
   9
  10 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  11                                              soc_sdram_argdict)
  12 from litex.soc.integration.builder import (Builder, builder_args,
  13                                            builder_argdict)
  14
  15 from libresoc import LibreSoC
  16 #from microwatt import Microwatt
  17
  18 # HACK!
  19 from litex.soc.integration.soc import SoCCSRHandler
  20 SoCCSRHandler.supported_address_width.append(12)
  21
  22
  23 # TestSoC
  24 # ----------------------------------------------------------------------------
  25
  26 from litex.build.generic_platform import Subsignal, Pins, IOStandard
  27
  28 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
  29     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  30         kwargs["integrated_rom_size"] = 0x10000
  31         #kwargs["integrated_main_ram_size"] = 0x1000
  32         kwargs["csr_data_width"] = 32
  33         kwargs['csr_address_width'] = 15 # limit to 0x8000
  34         kwargs["l2_size"] = 0
  35         #bus_data_width = 16,
  36
  37         versa_ecp5.BaseSoC.__init__(self,
  38             sys_clk_freq = sys_clk_freq,
  39             cpu_type     = "external",
  40             cpu_cls      = LibreSoC,
  41             cpu_variant = "standardjtagnoirq",
  42             #cpu_cls      = Microwatt,
  43             device       = "LFE5UM",
  44             **kwargs)
  45
  46         # (thanks to daveshah for this tip)
  47         # use platform.add_extension to first define the pins
  48         # https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134
  49
  50         # define the pins, add as an extension, *then* request it
  51         jtag_ios = [
  52             ("jtag", 0,
  53                 Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS33")),
  54                 Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
  55                 Subsignal("tck", Pins("B9"), IOStandard("LVCMOS33")),
  56                 Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
  57             )
  58         ]
  59         self.platform.add_extension(jtag_ios)
  60         jtag = self.platform.request("jtag")
  61
  62         # wire the pins up to CPU JTAG
  63         self.comb += self.cpu.jtag_tck.eq(jtag.tck)
  64         self.comb += self.cpu.jtag_tms.eq(jtag.tms)
  65         self.comb += self.cpu.jtag_tdi.eq(jtag.tdi)
  66         self.comb += jtag.tdo.eq(self.cpu.jtag_tdo)
  67
  68
  69         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  70         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  71         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  72
  73         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  74         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  75         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  76
  77
  78 class ULX3S85FTestSoC(ulx3s.BaseSoC):
  79     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  80         kwargs["integrated_rom_size"] = 0x10000
  81         #kwargs["integrated_main_ram_size"] = 0x1000
  82         kwargs["csr_data_width"] = 32
  83         kwargs["l2_size"] = 0
  84         #bus_data_width = 16,
  85
  86         ulx3s.BaseSoC.__init__(self,
  87             sys_clk_freq = sys_clk_freq,
  88             cpu_type     = "external",
  89             cpu_cls      = LibreSoC,
  90             cpu_variant  = "standardjtag",
  91             #cpu_cls      = Microwatt,
  92             device       = "LFE5U-85F",
  93             **kwargs)
  94
  95         # get 4 arbitrarily assinged logical pins, each gpio has
  96         # 2 distinct physical single non-differential pins p and n
  97         gpio0    = self.platform.request("gpio", 0)
  98         gpio1    = self.platform.request("gpio", 1)
  99
 100         # assign p, n litex 'subsignals' of each gpio to jtag pins
 101         jtag_tdi = gpio0.n
 102         jtag_tms = gpio0.p
 103         jtag_tck = gpio1.n
 104         jtag_tdo = gpio1.p
 105
 106         # wire the pins up to CPU JTAG
 107         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 108         self.comb += self.cpu.jtag_tms.eq(jtag_tms)
 109         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 110         self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
 111
 112 # Build
 113 # ----------------------------------------------------------------------------
 114
 115 def main():
 116     parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
 117                                      "CPU on Versa ECP5 or ULX3S LFE5U85F")
 118     parser.add_argument("--build", action="store_true", help="Build bitstream")
 119     parser.add_argument("--load", action="store_true", help="Load bitstream")
 120     parser.add_argument("--sys-clk-freq",  default=int(16e6),
 121                         help="System clock frequency (default=16MHz)")
 122     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
 123                         "to build for/load to")
 124     parser.add_argument("--load-from", default=None, help="svf to load, disables build")
 125
 126     builder_args(parser)
 127     soc_sdram_args(parser)
 128     args = parser.parse_args()
 129
 130     if args.fpga == "versa_ecp5":
 131         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 132                                **soc_sdram_argdict(args))
 133
 134     elif args.fpga == "ulx3s85f":
 135         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 136                               **soc_sdram_argdict(args))
 137
 138     else:
 139         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 140                                **soc_sdram_argdict(args))
 141
 142     if args.load_from == None:
 143         builder = Builder(soc, **builder_argdict(args))
 144         builder.build(run=args.build)
 145
 146         if args.load:
 147             prog = soc.platform.create_programmer()
 148             prog.load_bitstream(os.path.join(builder.gateware_dir,
 149                                            soc.build_name + ".svf"))
 150     else:
 151         if args.load or args.build:
 152             print("--load-from is incompatible with --load and --build", file=sys.stderr)
 153             sys.exit(1)
 154         prog = soc.platform.create_programmer()
 155         prog.load_bitstream(args.load_from)
 156
 157 if __name__ == "__main__":
 158     main()