versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5 import sys
   6
   7 import litex_boards.targets.versa_ecp5 as versa_ecp5
   8 import litex_boards.targets.ulx3s as ulx3s
   9 #import litex_boards.targets.arty as arty
  10 import digilent_arty as arty
  11
  12 from litex.build.lattice.trellis import trellis_args, trellis_argdict
  13
  14 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  15                                              soc_sdram_argdict)
  16 from litex.soc.integration.builder import (Builder, builder_args,
  17                                            builder_argdict)
  18
  19 from libresoc import LibreSoC
  20 #from microwatt import Microwatt
  21
  22 # HACK!
  23 from litex.soc.integration.soc import SoCCSRHandler
  24 SoCCSRHandler.supported_address_width.append(12)
  25
  26
  27 # TestSoC
  28 # ----------------------------------------------------------------------------
  29
  30 from litex.build.generic_platform import Subsignal, Pins, IOStandard
  31
  32 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
  33     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  34         kwargs["integrated_rom_size"] = 0x10000
  35         #kwargs["integrated_main_ram_size"] = 0x1000
  36         kwargs["csr_data_width"] = 32
  37         kwargs['csr_address_width'] = 15 # limit to 0x8000
  38         kwargs["l2_size"] = 0
  39         #bus_data_width = 16,
  40
  41         versa_ecp5.BaseSoC.__init__(self,
  42             sys_clk_freq = sys_clk_freq,
  43             cpu_type     = "external",
  44             cpu_cls      = LibreSoC,
  45             cpu_variant = "standardjtagnoirq",
  46             #cpu_cls      = Microwatt,
  47             device       = "LFE5UM",
  48             **kwargs)
  49
  50         # (thanks to daveshah for this tip)
  51         # use platform.add_extension to first define the pins
  52         # https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134
  53
  54         # define the pins, add as an extension, *then* request it
  55         jtag_ios = [
  56             ("jtag", 0,
  57                 Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS33")),
  58                 Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
  59                 Subsignal("tck", Pins("B9"), IOStandard("LVCMOS33")),
  60                 Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
  61             )
  62         ]
  63         self.platform.add_extension(jtag_ios)
  64         jtag = self.platform.request("jtag")
  65
  66         # wire the pins up to CPU JTAG
  67         self.comb += self.cpu.jtag_tck.eq(jtag.tck)
  68         self.comb += self.cpu.jtag_tms.eq(jtag.tms)
  69         self.comb += self.cpu.jtag_tdi.eq(jtag.tdi)
  70         self.comb += jtag.tdo.eq(self.cpu.jtag_tdo)
  71
  72
  73         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  74         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  75         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  76
  77         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  78         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  79         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  80
  81
  82 class ULX3S85FTestSoC(ulx3s.BaseSoC):
  83     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  84         kwargs["integrated_rom_size"] = 0x10000
  85         #kwargs["integrated_main_ram_size"] = 0x1000
  86         kwargs["csr_data_width"] = 32
  87         kwargs["l2_size"] = 0
  88         #bus_data_width = 16,
  89
  90         ulx3s.BaseSoC.__init__(self,
  91             sys_clk_freq = sys_clk_freq,
  92             cpu_type     = "external",
  93             cpu_cls      = LibreSoC,
  94             cpu_variant  = "standardjtag",
  95             #cpu_cls      = Microwatt,
  96             device       = "LFE5U-85F",
  97             **kwargs)
  98
  99         # get 4 arbitrarily assinged logical pins, each gpio has
 100         # 2 distinct physical single non-differential pins p and n
 101         gpio0    = self.platform.request("gpio", 0)
 102         gpio1    = self.platform.request("gpio", 1)
 103
 104         # assign p, n litex 'subsignals' of each gpio to jtag pins
 105         jtag_tdi = gpio0.n
 106         jtag_tms = gpio0.p
 107         jtag_tck = gpio1.n
 108         jtag_tdo = gpio1.p
 109
 110         # wire the pins up to CPU JTAG
 111         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 112         self.comb += self.cpu.jtag_tms.eq(jtag_tms)
 113         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 114         self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
 115
 116
 117 class ArtyTestSoC(arty.BaseSoC):
 118     def __init__(self, sys_clk_freq=int(100e6), **kwargs):
 119         kwargs["integrated_rom_size"] = 0x10000
 120         #kwargs["integrated_main_ram_size"] = 0x1000
 121         kwargs["csr_data_width"] = 32
 122         kwargs['csr_address_width'] = 15 # limit to 0x8000
 123         kwargs["l2_size"] = 0
 124         #bus_data_width = 16,
 125
 126         arty.BaseSoC.__init__(self,
 127             sys_clk_freq = sys_clk_freq,
 128             cpu_type     = "external",
 129             cpu_cls      = LibreSoC,
 130             cpu_variant  = "standardjtag",
 131             #cpu_cls      = Microwatt,
 132             variant      = "a7-100",
 133             toolchain    = "symbiflow",
 134             **kwargs)
 135
 136
 137 # Build
 138 # ----------------------------------------------------------------------------
 139
 140 def main():
 141     parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
 142                                      "CPU on Versa ECP5 or ULX3S LFE5U85F")
 143     parser.add_argument("--build", action="store_true", help="Build bitstream")
 144     parser.add_argument("--load", action="store_true", help="Load bitstream")
 145     parser.add_argument("--sys-clk-freq",  default=int(16e6),
 146                         help="System clock frequency (default=16MHz)")
 147     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
 148                         "to build for/load to")
 149     parser.add_argument("--load-from", default=None, help="svf to load, disables build")
 150     parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
 151
 152     builder_args(parser)
 153     soc_sdram_args(parser)
 154     args = parser.parse_args()
 155
 156     if args.fpga == "versa_ecp5":
 157         trellis_args(parser)
 158         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 159                                **soc_sdram_argdict(args))
 160
 161     elif args.fpga == "ulx3s85f":
 162         trellis_args(parser)
 163         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 164                               **soc_sdram_argdict(args))
 165
 166     elif args.fpga == "artya7100t":
 167         soc = ArtyTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 168                               **soc_sdram_argdict(args))
 169
 170     else:
 171         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 172                                **soc_sdram_argdict(args))
 173
 174     if args.load_from == None:
 175         builder = Builder(soc, **builder_argdict(args))
 176         builder_kargs = trellis_argdict(args) \
 177                 if args.toolchain == "trellis" else {}
 178         builder.build(**builder_kargs, run=args.build)
 179
 180         if args.load:
 181             prog = soc.platform.create_programmer()
 182             prog.load_bitstream(os.path.join(builder.gateware_dir,
 183                                            soc.build_name + ".svf"))
 184     else:
 185         if args.load or args.build:
 186             print("--load-from is incompatible with --load and --build", file=sys.stderr)
 187             sys.exit(1)
 188         prog = soc.platform.create_programmer()
 189         prog.load_bitstream(args.load_from)
 190
 191 if __name__ == "__main__":
 192     main()