wishbone_bram_wrapper.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use std.textio.all;
   5
   6 library work;
   7 use work.utils.all;
   8 use work.wishbone_types.all;
   9
  10 --! @brief Simple memory module for use in Wishbone-based systems.
  11 entity wishbone_bram_wrapper is
  12     generic(
  13         MEMORY_SIZE   : natural := 4096; --! Memory size in bytes.
  14         RAM_INIT_FILE : string;
  15     SIM_MAIN_BRAM : boolean := false
  16         );
  17     port(
  18         clk : in std_logic;
  19         rst : in std_logic;
  20
  21         -- Wishbone interface:
  22         wishbone_in  : in wishbone_master_out;
  23         wishbone_out : out wishbone_slave_out;
  24
  25     -- BRAM verilator access
  26     bram_we : out std_ulogic;
  27     bram_re : out std_ulogic;
  28     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
  29     bram_di   : out std_logic_vector(63 downto 0);
  30     bram_do   : in std_logic_vector(63 downto 0);
  31     bram_sel  : out std_logic_vector(7 downto 0)
  32
  33         );
  34 end entity wishbone_bram_wrapper;
  35
  36 architecture behaviour of wishbone_bram_wrapper is
  37     constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
  38
  39     -- RAM interface
  40     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
  41     signal ram_we   : std_ulogic;
  42     signal ram_re   : std_ulogic;
  43
  44     -- Others
  45     signal ack, ack_buf : std_ulogic;
  46 begin
  47
  48     -- Actual RAM template
  49     sim_ram: if SIM_MAIN_BRAM = true generate
  50         ram_0: entity work.main_bram
  51         generic map(
  52             WIDTH => 64,
  53             HEIGHT_BITS => ram_addr_bits,
  54             MEMORY_SIZE => MEMORY_SIZE,
  55             RAM_INIT_FILE => RAM_INIT_FILE
  56             )
  57         port map(
  58             clk => clk,
  59             addr => ram_addr,
  60             di => wishbone_in.dat,
  61             do => wishbone_out.dat,
  62             sel => wishbone_in.sel,
  63             re => ram_re,
  64             we => ram_we
  65             );
  66     end generate;
  67
  68     -- Verilator access to bram signals
  69     bram_sel <= wishbone_in.sel;
  70     wishbone_out.dat <= bram_do;
  71     bram_di <= wishbone_in.dat;
  72     bram_addr <= ram_addr;
  73     bram_we <= ram_we;
  74     bram_re <= ram_re;
  75
  76     -- Wishbone interface
  77     ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
  78     ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
  79     ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
  80     wishbone_out.stall <= '0';
  81     wishbone_out.ack <= ack_buf;
  82
  83     wb_0: process(clk)
  84     begin
  85         if rising_edge(clk) then
  86             if rst = '1' or wishbone_in.cyc = '0' then
  87                 ack_buf <= '0';
  88                 ack <= '0';
  89             else
  90                 -- On loads, we have a delay cycle due to BRAM bufferring
  91                 -- but not on stores. So try to send an early ack on a
  92                 -- store if we aren't behind an existing load ack.
  93                 --
  94                 if ram_we = '1' and ack = '0' then
  95                     ack_buf <= '1';
  96                 else
  97                     ack <= wishbone_in.stb;
  98                     ack_buf <= ack;
  99                 end if;
 100             end if;
 101         end if;
 102     end process;
 103
 104 end architecture behaviour;