wishbone_types.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 package wishbone_types is
   5     --
   6     -- Main CPU bus. 32-bit address, 64-bit data,
   7     -- so the wishbone address is in units of 8 bytes.
   8     --
   9     constant wishbone_addr_bits : integer := 29;
  10     constant wishbone_data_bits : integer := 64;
  11     constant wishbone_sel_bits : integer := wishbone_data_bits/8;
  12     constant wishbone_log2_width : integer := 3;
  13
  14     subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
  15     subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
  16     subtype wishbone_sel_type  is std_ulogic_vector(wishbone_sel_bits-1  downto 0);
  17
  18     function addr_to_wb(addr: std_ulogic_vector) return wishbone_addr_type;
  19     function wb_to_addr(wb_addr: wishbone_addr_type) return std_ulogic_vector;
  20
  21     type wishbone_master_out is record
  22         adr : wishbone_addr_type;
  23         dat : wishbone_data_type;
  24         sel : wishbone_sel_type;
  25         cyc : std_ulogic;
  26         stb : std_ulogic;
  27         we  : std_ulogic;
  28     end record;
  29     constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');
  30
  31     type wishbone_slave_out is record
  32         dat   : wishbone_data_type;
  33         ack   : std_ulogic;
  34         stall : std_ulogic;
  35     end record;
  36     constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));
  37
  38     type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
  39     type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
  40
  41     --
  42     -- IO Bus to a device, 30-bit address, 32-bits data
  43     --
  44
  45     type wb_io_master_out is record
  46         adr : std_ulogic_vector(29 downto 0);
  47         dat : std_ulogic_vector(31 downto 0);
  48         sel : std_ulogic_vector(3 downto 0);
  49         cyc : std_ulogic;
  50         stb : std_ulogic;
  51         we  : std_ulogic;
  52     end record;
  53     constant wb_io_master_out_init : wb_io_master_out := (adr => (others => '0'), dat => (others => '0'),
  54                                                           sel => "0000", cyc => '0', stb => '0', we => '0');
  55
  56     type wb_io_slave_out is record
  57         dat   : std_ulogic_vector(31 downto 0);
  58         ack   : std_ulogic;
  59         stall : std_ulogic;
  60     end record;
  61     constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
  62 end package wishbone_types;
  63
  64 package body wishbone_types is
  65     function addr_to_wb(addr: std_ulogic_vector) return wishbone_addr_type is
  66     begin
  67         assert addr'length >= (wishbone_addr_type'length + wishbone_log2_width);
  68         assert addr'right = 0;
  69         return addr(wishbone_addr_type'left + wishbone_log2_width downto wishbone_log2_width);
  70     end;
  71     function wb_to_addr(wb_addr: wishbone_addr_type) return std_ulogic_vector is
  72         variable ret  : std_ulogic_vector(63 downto 0);
  73     begin
  74         ret := (others => '0');
  75         ret(wishbone_addr_type'left + wishbone_log2_width downto wishbone_log2_width) := wb_addr;
  76         return ret;
  77     end;
  78 end wishbone_types;