xilinx-mult.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 library unisim;
   9 use unisim.vcomponents.all;
  10
  11 entity multiply is
  12     port (
  13         clk   : in std_logic;
  14
  15         m_in  : in MultiplyInputType;
  16         m_out : out MultiplyOutputType
  17         );
  18 end entity multiply;
  19
  20 architecture behaviour of multiply is
  21     signal m00_p, m01_p, m02_p, m03_p : std_ulogic_vector(47 downto 0);
  22     signal m00_pc : std_ulogic_vector(47 downto 0);
  23     signal m10_p, m11_p, m12_p, m13_p : std_ulogic_vector(47 downto 0);
  24     signal m11_pc, m12_pc, m13_pc : std_ulogic_vector(47 downto 0);
  25     signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
  26     signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
  27     signal product : std_ulogic_vector(127 downto 0);
  28     signal addend : std_ulogic_vector(127 downto 0);
  29     signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
  30     signal p0_mask : std_ulogic_vector(47 downto 0);
  31     signal p0_pat, p0_patb : std_ulogic;
  32     signal p1_pat, p1_patb : std_ulogic;
  33
  34     signal req_32bit, r32_1 : std_ulogic;
  35     signal rnot_1 : std_ulogic;
  36     signal valid_1 : std_ulogic;
  37     signal overflow, ovf_in : std_ulogic;
  38
  39 begin
  40     addend <= m_in.addend;
  41
  42     m00: DSP48E1
  43         generic map (
  44             ACASCREG => 0,
  45             ALUMODEREG => 0,
  46             AREG => 0,
  47             BCASCREG => 0,
  48             BREG => 0,
  49             CARRYINREG => 0,
  50             CARRYINSELREG => 0,
  51             CREG => 0,
  52             INMODEREG => 0,
  53             MREG => 0,
  54             OPMODEREG => 0,
  55             PREG => 1
  56             )
  57         port map (
  58             A => "0000000" & m_in.data1(22 downto 0),
  59             ACIN => (others => '0'),
  60             ALUMODE => "0000",
  61             B => '0' & m_in.data2(16 downto 0),
  62             BCIN => (others => '0'),
  63             C => "00000000000000" & addend(33 downto 0),
  64             CARRYCASCIN => '0',
  65             CARRYIN => '0',
  66             CARRYINSEL => "000",
  67             CEA1 => '0',
  68             CEA2 => '0',
  69             CEAD => '0',
  70             CEALUMODE => '0',
  71             CEB1 => '0',
  72             CEB2 => '0',
  73             CEC => '0',
  74             CECARRYIN => '0',
  75             CECTRL => '0',
  76             CED => '0',
  77             CEINMODE => '0',
  78             CEM => '0',
  79             CEP => m_in.valid,
  80             CLK => clk,
  81             D => (others => '0'),
  82             INMODE => "00000",
  83             MULTSIGNIN => '0',
  84             OPMODE => "0110101",
  85             P => m00_p,
  86             PCIN => (others => '0'),
  87             PCOUT => m00_pc,
  88             RSTA => '0',
  89             RSTALLCARRYIN => '0',
  90             RSTALUMODE => '0',
  91             RSTB => '0',
  92             RSTC => '0',
  93             RSTCTRL => '0',
  94             RSTD => '0',
  95             RSTINMODE => '0',
  96             RSTM => '0',
  97             RSTP => '0'
  98             );
  99
 100     m01: DSP48E1
 101         generic map (
 102             ACASCREG => 0,
 103             ALUMODEREG => 0,
 104             AREG => 0,
 105             BCASCREG => 0,
 106             BREG => 0,
 107             CARRYINREG => 0,
 108             CARRYINSELREG => 0,
 109             INMODEREG => 0,
 110             OPMODEREG => 0,
 111             PREG => 0
 112             )
 113         port map (
 114             A => "0000000" & m_in.data1(22 downto 0),
 115             ACIN => (others => '0'),
 116             ALUMODE => "0000",
 117             B => '0' & m_in.data2(33 downto 17),
 118             BCIN => (others => '0'),
 119             C => (others => '0'),
 120             CARRYCASCIN => '0',
 121             CARRYIN => '0',
 122             CARRYINSEL => "000",
 123             CEA1 => '0',
 124             CEA2 => '0',
 125             CEAD => '0',
 126             CEALUMODE => '0',
 127             CEB1 => '0',
 128             CEB2 => '0',
 129             CEC => '1',
 130             CECARRYIN => '0',
 131             CECTRL => '0',
 132             CED => '0',
 133             CEINMODE => '0',
 134             CEM => m_in.valid,
 135             CEP => '0',
 136             CLK => clk,
 137             D => (others => '0'),
 138             INMODE => "00000",
 139             MULTSIGNIN => '0',
 140             OPMODE => "1010101",
 141             P => m01_p,
 142             PCIN => m00_pc,
 143             RSTA => '0',
 144             RSTALLCARRYIN => '0',
 145             RSTALUMODE => '0',
 146             RSTB => '0',
 147             RSTC => '0',
 148             RSTCTRL => '0',
 149             RSTD => '0',
 150             RSTINMODE => '0',
 151             RSTM => '0',
 152             RSTP => '0'
 153             );
 154
 155     m02: DSP48E1
 156         generic map (
 157             ACASCREG => 0,
 158             ALUMODEREG => 0,
 159             AREG => 0,
 160             BCASCREG => 0,
 161             BREG => 0,
 162             CARRYINREG => 0,
 163             CARRYINSELREG => 0,
 164             CREG => 0,
 165             INMODEREG => 0,
 166             MREG => 0,
 167             OPMODEREG => 0,
 168             PREG => 1
 169             )
 170         port map (
 171             A => "0000000" & m_in.data1(22 downto 0),
 172             ACIN => (others => '0'),
 173             ALUMODE => "0000",
 174             B => '0' & m_in.data2(50 downto 34),
 175             BCIN => (others => '0'),
 176             C => x"0000000" & "000" & addend(50 downto 34),
 177             CARRYCASCIN => '0',
 178             CARRYIN => '0',
 179             CARRYINSEL => "000",
 180             CEA1 => '0',
 181             CEA2 => '0',
 182             CEAD => '0',
 183             CEALUMODE => '0',
 184             CEB1 => '0',
 185             CEB2 => '0',
 186             CEC => '0',
 187             CECARRYIN => '0',
 188             CECTRL => '0',
 189             CED => '0',
 190             CEINMODE => '0',
 191             CEM => '0',
 192             CEP => m_in.valid,
 193             CLK => clk,
 194             D => (others => '0'),
 195             INMODE => "00000",
 196             MULTSIGNIN => '0',
 197             OPMODE => "0110101",
 198             P => m02_p,
 199             PCIN => (others => '0'),
 200             RSTA => '0',
 201             RSTALLCARRYIN => '0',
 202             RSTALUMODE => '0',
 203             RSTB => '0',
 204             RSTC => '0',
 205             RSTCTRL => '0',
 206             RSTD => '0',
 207             RSTINMODE => '0',
 208             RSTM => '0',
 209             RSTP => '0'
 210             );
 211
 212     m03: DSP48E1
 213         generic map (
 214             ACASCREG => 0,
 215             ALUMODEREG => 0,
 216             AREG => 0,
 217             BCASCREG => 0,
 218             BREG => 0,
 219             CARRYINREG => 0,
 220             CARRYINSELREG => 0,
 221             CREG => 0,
 222             INMODEREG => 0,
 223             MREG => 0,
 224             OPMODEREG => 0,
 225             PREG => 1
 226             )
 227         port map (
 228             A => "0000000" & m_in.data1(22 downto 0),
 229             ACIN => (others => '0'),
 230             ALUMODE => "0000",
 231             B => "00000" & m_in.data2(63 downto 51),
 232             BCIN => (others => '0'),
 233             C => x"000000" & '0' & addend(73 downto 51),
 234             CARRYCASCIN => '0',
 235             CARRYIN => '0',
 236             CARRYINSEL => "000",
 237             CEA1 => '0',
 238             CEA2 => '0',
 239             CEAD => '0',
 240             CEALUMODE => '0',
 241             CEB1 => '0',
 242             CEB2 => '0',
 243             CEC => '0',
 244             CECARRYIN => '0',
 245             CECTRL => '0',
 246             CED => '0',
 247             CEINMODE => '0',
 248             CEM => '0',
 249             CEP => m_in.valid,
 250             CLK => clk,
 251             D => (others => '0'),
 252             INMODE => "00000",
 253             MULTSIGNIN => '0',
 254             OPMODE => "0110101",
 255             P => m03_p,
 256             PCIN => (others => '0'),
 257             RSTA => '0',
 258             RSTALLCARRYIN => '0',
 259             RSTALUMODE => '0',
 260             RSTB => '0',
 261             RSTC => '0',
 262             RSTCTRL => '0',
 263             RSTD => '0',
 264             RSTINMODE => '0',
 265             RSTM => '0',
 266             RSTP => '0'
 267             );
 268
 269     m10: DSP48E1
 270         generic map (
 271             ACASCREG => 0,
 272             ALUMODEREG => 0,
 273             AREG => 0,
 274             BCASCREG => 0,
 275             BREG => 0,
 276             CARRYINREG => 0,
 277             CARRYINSELREG => 0,
 278             CREG => 0,
 279             INMODEREG => 0,
 280             OPMODEREG => 0,
 281             PREG => 0
 282             )
 283         port map (
 284             A => "0000000000000" & m_in.data1(39 downto 23),
 285             ACIN => (others => '0'),
 286             ALUMODE => "0000",
 287             B => '0' & m_in.data2(16 downto 0),
 288             BCIN => (others => '0'),
 289             C => x"000" & "00" & m01_p(39 downto 6),
 290             CARRYCASCIN => '0',
 291             CARRYIN => '0',
 292             CARRYINSEL => "000",
 293             CEA1 => '0',
 294             CEA2 => '0',
 295             CEAD => '0',
 296             CEALUMODE => '0',
 297             CEB1 => '0',
 298             CEB2 => '0',
 299             CEC => '0',
 300             CECARRYIN => '0',
 301             CECTRL => '0',
 302             CED => '0',
 303             CEINMODE => '0',
 304             CEM => m_in.valid,
 305             CEP => '0',
 306             CLK => clk,
 307             D => (others => '0'),
 308             INMODE => "00000",
 309             MULTSIGNIN => '0',
 310             OPMODE => "0110101",
 311             P => m10_p,
 312             PCIN => (others => '0'),
 313             RSTA => '0',
 314             RSTALLCARRYIN => '0',
 315             RSTALUMODE => '0',
 316             RSTB => '0',
 317             RSTC => '0',
 318             RSTCTRL => '0',
 319             RSTD => '0',
 320             RSTINMODE => '0',
 321             RSTM => '0',
 322             RSTP => '0'
 323             );
 324
 325     m11: DSP48E1
 326         generic map (
 327             ACASCREG => 0,
 328             ALUMODEREG => 0,
 329             AREG => 0,
 330             BCASCREG => 0,
 331             BREG => 0,
 332             CARRYINREG => 0,
 333             CARRYINSELREG => 0,
 334             CREG => 0,
 335             INMODEREG => 0,
 336             OPMODEREG => 0,
 337             PREG => 0
 338             )
 339         port map (
 340             A => "0000000000000" & m_in.data1(39 downto 23),
 341             ACIN => (others => '0'),
 342             ALUMODE => "0000",
 343             B => '0' & m_in.data2(33 downto 17),
 344             BCIN => (others => '0'),
 345             C => x"000" & "00" & m02_p(39 downto 6),
 346             CARRYCASCIN => '0',
 347             CARRYIN => '0',
 348             CARRYINSEL => "000",
 349             CEA1 => '0',
 350             CEA2 => '0',
 351             CEAD => '0',
 352             CEALUMODE => '0',
 353             CEB1 => '0',
 354             CEB2 => '0',
 355             CEC => '0',
 356             CECARRYIN => '0',
 357             CECTRL => '0',
 358             CED => '0',
 359             CEINMODE => '0',
 360             CEM => m_in.valid,
 361             CEP => '0',
 362             CLK => clk,
 363             D => (others => '0'),
 364             INMODE => "00000",
 365             MULTSIGNIN => '0',
 366             OPMODE => "0110101",
 367             P => m11_p,
 368             PCIN => (others => '0'),
 369             PCOUT => m11_pc,
 370             RSTA => '0',
 371             RSTALLCARRYIN => '0',
 372             RSTALUMODE => '0',
 373             RSTB => '0',
 374             RSTC => '0',
 375             RSTCTRL => '0',
 376             RSTD => '0',
 377             RSTINMODE => '0',
 378             RSTM => '0',
 379             RSTP => '0'
 380             );
 381
 382     m12: DSP48E1
 383         generic map (
 384             ACASCREG => 0,
 385             ALUMODEREG => 0,
 386             AREG => 0,
 387             BCASCREG => 0,
 388             BREG => 0,
 389             CARRYINREG => 0,
 390             CARRYINSELREG => 0,
 391             CREG => 0,
 392             INMODEREG => 0,
 393             OPMODEREG => 0,
 394             PREG => 0
 395             )
 396         port map (
 397             A => "0000000000000" & m_in.data1(39 downto 23),
 398             ACIN => (others => '0'),
 399             ALUMODE => "0000",
 400             B => '0' & m_in.data2(50 downto 34),
 401             BCIN => (others => '0'),
 402             C => x"0000" & '0' & m03_p(36 downto 6),
 403             CARRYCASCIN => '0',
 404             CARRYIN => '0',
 405             CARRYINSEL => "000",
 406             CEA1 => '0',
 407             CEA2 => '0',
 408             CEAD => '0',
 409             CEALUMODE => '0',
 410             CEB1 => '0',
 411             CEB2 => '0',
 412             CEC => '0',
 413             CECARRYIN => '0',
 414             CECTRL => '0',
 415             CED => '0',
 416             CEINMODE => '0',
 417             CEM => m_in.valid,
 418             CEP => '0',
 419             CLK => clk,
 420             D => (others => '0'),
 421             INMODE => "00000",
 422             MULTSIGNIN => '0',
 423             OPMODE => "0110101",
 424             P => m12_p,
 425             PCIN => (others => '0'),
 426             PCOUT => m12_pc,
 427             RSTA => '0',
 428             RSTALLCARRYIN => '0',
 429             RSTALUMODE => '0',
 430             RSTB => '0',
 431             RSTC => '0',
 432             RSTCTRL => '0',
 433             RSTD => '0',
 434             RSTINMODE => '0',
 435             RSTM => '0',
 436             RSTP => '0'
 437             );
 438
 439     m13: DSP48E1
 440         generic map (
 441             ACASCREG => 0,
 442             ALUMODEREG => 0,
 443             AREG => 0,
 444             BCASCREG => 0,
 445             BREG => 0,
 446             CARRYINREG => 0,
 447             CARRYINSELREG => 0,
 448             INMODEREG => 0,
 449             OPMODEREG => 0,
 450             PREG => 0
 451             )
 452         port map (
 453             A => "0000000000000" & m_in.data1(39 downto 23),
 454             ACIN => (others => '0'),
 455             ALUMODE => "0000",
 456             B => "00000" & m_in.data2(63 downto 51),
 457             BCIN => (others => '0'),
 458             C => x"0000000" & "000" & addend(90 downto 74),
 459             CARRYCASCIN => '0',
 460             CARRYIN => '0',
 461             CARRYINSEL => "000",
 462             CEA1 => '0',
 463             CEA2 => '0',
 464             CEAD => '0',
 465             CEALUMODE => '0',
 466             CEB1 => '0',
 467             CEB2 => '0',
 468             CEC => '1',
 469             CECARRYIN => '0',
 470             CECTRL => '0',
 471             CED => '0',
 472             CEINMODE => '0',
 473             CEM => m_in.valid,
 474             CEP => '0',
 475             CLK => clk,
 476             D => (others => '0'),
 477             INMODE => "00000",
 478             MULTSIGNIN => '0',
 479             OPMODE => "0110101",
 480             P => m13_p,
 481             PCIN => (others => '0'),
 482             PCOUT => m13_pc,
 483             RSTA => '0',
 484             RSTALLCARRYIN => '0',
 485             RSTALUMODE => '0',
 486             RSTB => '0',
 487             RSTC => '0',
 488             RSTCTRL => '0',
 489             RSTD => '0',
 490             RSTINMODE => '0',
 491             RSTM => '0',
 492             RSTP => '0'
 493             );
 494
 495     m20: DSP48E1
 496         generic map (
 497             ACASCREG => 0,
 498             ALUMODEREG => 0,
 499             AREG => 0,
 500             BCASCREG => 0,
 501             BREG => 0,
 502             CARRYINREG => 0,
 503             CARRYINSELREG => 0,
 504             INMODEREG => 0,
 505             OPMODEREG => 0,
 506             PREG => 0
 507             )
 508         port map (
 509             A => "000000" & m_in.data1(63 downto 40),
 510             ACIN => (others => '0'),
 511             ALUMODE => "0000",
 512             B => '0' & m_in.data2(16 downto 0),
 513             BCIN => (others => '0'),
 514             C => (others => '0'),
 515             CARRYCASCIN => '0',
 516             CARRYIN => '0',
 517             CARRYINSEL => "000",
 518             CEA1 => '0',
 519             CEA2 => '0',
 520             CEAD => '0',
 521             CEALUMODE => '0',
 522             CEB1 => '0',
 523             CEB2 => '0',
 524             CEC => '1',
 525             CECARRYIN => '0',
 526             CECTRL => '0',
 527             CED => '0',
 528             CEINMODE => '0',
 529             CEM => m_in.valid,
 530             CEP => '0',
 531             CLK => clk,
 532             D => (others => '0'),
 533             INMODE => "00000",
 534             MULTSIGNIN => '0',
 535             OPMODE => "0010101",
 536             P => m20_p,
 537             PCIN => m11_pc,
 538             RSTA => '0',
 539             RSTALLCARRYIN => '0',
 540             RSTALUMODE => '0',
 541             RSTB => '0',
 542             RSTC => '0',
 543             RSTCTRL => '0',
 544             RSTD => '0',
 545             RSTINMODE => '0',
 546             RSTM => '0',
 547             RSTP => '0'
 548             );
 549
 550     m21: DSP48E1
 551         generic map (
 552             ACASCREG => 0,
 553             ALUMODEREG => 0,
 554             AREG => 0,
 555             BCASCREG => 0,
 556             BREG => 0,
 557             CARRYINREG => 0,
 558             CARRYINSELREG => 0,
 559             INMODEREG => 0,
 560             OPMODEREG => 0,
 561             PREG => 0
 562             )
 563         port map (
 564             A => "000000" & m_in.data1(63 downto 40),
 565             ACIN => (others => '0'),
 566             ALUMODE => "0000",
 567             B => '0' & m_in.data2(33 downto 17),
 568             BCIN => (others => '0'),
 569             C => (others => '0'),
 570             CARRYCASCIN => '0',
 571             CARRYIN => '0',
 572             CARRYINSEL => "000",
 573             CEA1 => '0',
 574             CEA2 => '0',
 575             CEAD => '0',
 576             CEALUMODE => '0',
 577             CEB1 => '0',
 578             CEB2 => '0',
 579             CEC => '1',
 580             CECARRYIN => '0',
 581             CECTRL => '0',
 582             CED => '0',
 583             CEINMODE => '0',
 584             CEM => m_in.valid,
 585             CEP => '0',
 586             CLK => clk,
 587             D => (others => '0'),
 588             INMODE => "00000",
 589             MULTSIGNIN => '0',
 590             OPMODE => "0010101",
 591             P => m21_p,
 592             PCIN => m12_pc,
 593             RSTA => '0',
 594             RSTALLCARRYIN => '0',
 595             RSTALUMODE => '0',
 596             RSTB => '0',
 597             RSTC => '0',
 598             RSTCTRL => '0',
 599             RSTD => '0',
 600             RSTINMODE => '0',
 601             RSTM => '0',
 602             RSTP => '0'
 603             );
 604
 605     m22: DSP48E1
 606         generic map (
 607             ACASCREG => 0,
 608             ALUMODEREG => 0,
 609             AREG => 0,
 610             BCASCREG => 0,
 611             BREG => 0,
 612             CARRYINREG => 0,
 613             CARRYINSELREG => 0,
 614             INMODEREG => 0,
 615             OPMODEREG => 0,
 616             PREG => 0
 617             )
 618         port map (
 619             A => "000000" & m_in.data1(63 downto 40),
 620             ACIN => (others => '0'),
 621             ALUMODE => "0000",
 622             B => '0' & m_in.data2(50 downto 34),
 623             BCIN => (others => '0'),
 624             C => (others => '0'),
 625             CARRYCASCIN => '0',
 626             CARRYIN => '0',
 627             CARRYINSEL => "000",
 628             CEA1 => '0',
 629             CEA2 => '0',
 630             CEAD => '0',
 631             CEALUMODE => '0',
 632             CEB1 => '0',
 633             CEB2 => '0',
 634             CEC => '1',
 635             CECARRYIN => '0',
 636             CECTRL => '0',
 637             CED => '0',
 638             CEINMODE => '0',
 639             CEM => m_in.valid,
 640             CEP => '0',
 641             CLK => clk,
 642             D => (others => '0'),
 643             INMODE => "00000",
 644             MULTSIGNIN => '0',
 645             OPMODE => "0010101",
 646             P => m22_p,
 647             PCIN => m13_pc,
 648             RSTA => '0',
 649             RSTALLCARRYIN => '0',
 650             RSTALUMODE => '0',
 651             RSTB => '0',
 652             RSTC => '0',
 653             RSTCTRL => '0',
 654             RSTD => '0',
 655             RSTINMODE => '0',
 656             RSTM => '0',
 657             RSTP => '0'
 658             );
 659
 660     m23: DSP48E1
 661         generic map (
 662             ACASCREG => 0,
 663             ALUMODEREG => 0,
 664             AREG => 0,
 665             BCASCREG => 0,
 666             BREG => 0,
 667             CARRYINREG => 0,
 668             CARRYINSELREG => 0,
 669             INMODEREG => 0,
 670             OPMODEREG => 0,
 671             PREG => 0
 672             )
 673         port map (
 674             A => "000000" & m_in.data1(63 downto 40),
 675             ACIN => (others => '0'),
 676             ALUMODE => "0000",
 677             B => "00000" & m_in.data2(63 downto 51),
 678             BCIN => (others => '0'),
 679             C => x"00" & "000" & addend(127 downto 91),
 680             CARRYCASCIN => '0',
 681             CARRYIN => '0',
 682             CARRYINSEL => "000",
 683             CEA1 => '0',
 684             CEA2 => '0',
 685             CEAD => '0',
 686             CEALUMODE => '0',
 687             CEB1 => '0',
 688             CEB2 => '0',
 689             CEC => '1',
 690             CECARRYIN => '0',
 691             CECTRL => '0',
 692             CED => '0',
 693             CEINMODE => '0',
 694             CEM => m_in.valid,
 695             CEP => '0',
 696             CLK => clk,
 697             D => (others => '0'),
 698             INMODE => "00000",
 699             MULTSIGNIN => '0',
 700             OPMODE => "0110101",
 701             P => m23_p,
 702             PCIN => (others => '0'),
 703             RSTA => '0',
 704             RSTALLCARRYIN => '0',
 705             RSTALUMODE => '0',
 706             RSTB => '0',
 707             RSTC => '0',
 708             RSTCTRL => '0',
 709             RSTD => '0',
 710             RSTINMODE => '0',
 711             RSTM => '0',
 712             RSTP => '0'
 713             );
 714
 715     s0: DSP48E1
 716         generic map (
 717             ACASCREG => 0,
 718             ALUMODEREG => 0,
 719             AREG => 0,
 720             BCASCREG => 0,
 721             BREG => 0,
 722             CARRYINREG => 0,
 723             CARRYINSELREG => 0,
 724             CREG => 0,
 725             INMODEREG => 0,
 726             MREG => 0,
 727             OPMODEREG => 0,
 728             PREG => 1,
 729             USE_MULT => "none"
 730             )
 731         port map (
 732             A => m22_p(5 downto 0) & x"0000" & m10_p(34 downto 27),
 733             ACIN => (others => '0'),
 734             ALUMODE => "0000",
 735             B => m10_p(26 downto 9),
 736             BCIN => (others => '0'),
 737             C => m20_p(39 downto 0) & m02_p(5 downto 0) & "00",
 738             CARRYCASCIN => '0',
 739             CARRYIN => '0',
 740             CARRYINSEL => "000",
 741             CARRYOUT => s0_carry,
 742             CEA1 => '0',
 743             CEA2 => '0',
 744             CEAD => '0',
 745             CEALUMODE => '0',
 746             CEB1 => '0',
 747             CEB2 => '0',
 748             CEC => '0',
 749             CECARRYIN => '0',
 750             CECTRL => '0',
 751             CED => '0',
 752             CEINMODE => '0',
 753             CEM => '0',
 754             CEP => valid_1,
 755             CLK => clk,
 756             D => (others => '0'),
 757             INMODE => "00000",
 758             MULTSIGNIN => '0',
 759             OPMODE => "0001111",
 760             PCIN => (others => '0'),
 761             PCOUT => s0_pc,
 762             RSTA => '0',
 763             RSTALLCARRYIN => '0',
 764             RSTALUMODE => '0',
 765             RSTB => '0',
 766             RSTC => '0',
 767             RSTCTRL => '0',
 768             RSTD => '0',
 769             RSTINMODE => '0',
 770             RSTM => '0',
 771             RSTP => '0'
 772             );
 773
 774     s1: DSP48E1
 775         generic map (
 776             ACASCREG => 1,
 777             ALUMODEREG => 0,
 778             AREG => 1,
 779             BCASCREG => 1,
 780             BREG => 1,
 781             CARRYINREG => 0,
 782             CARRYINSELREG => 0,
 783             CREG => 1,
 784             INMODEREG => 0,
 785             MREG => 0,
 786             OPMODEREG => 0,
 787             PREG => 0,
 788             USE_MULT => "none"
 789             )
 790         port map (
 791             A => x"000" & m22_p(41 downto 24),
 792             ACIN => (others => '0'),
 793             ALUMODE => "0000",
 794             B => m22_p(23 downto 6),
 795             BCIN => (others => '0'),
 796             C => m23_p(36 downto 0) & x"00" & "0" & m20_p(41 downto 40),
 797             CARRYCASCIN => '0',
 798             CARRYIN => s0_carry(3),
 799             CARRYINSEL => "000",
 800             CEA1 => '0',
 801             CEA2 => valid_1,
 802             CEAD => '0',
 803             CEALUMODE => '0',
 804             CEB1 => '0',
 805             CEB2 => valid_1,
 806             CEC => valid_1,
 807             CECARRYIN => '0',
 808             CECTRL => '0',
 809             CED => '0',
 810             CEINMODE => '0',
 811             CEM => '0',
 812             CEP => '0',
 813             CLK => clk,
 814             D => (others => '0'),
 815             INMODE => "00000",
 816             MULTSIGNIN => '0',
 817             OPMODE => "0001111",
 818             PCIN => (others => '0'),
 819             PCOUT => s1_pc,
 820             RSTA => '0',
 821             RSTALLCARRYIN => '0',
 822             RSTALUMODE => '0',
 823             RSTB => '0',
 824             RSTC => '0',
 825             RSTCTRL => '0',
 826             RSTD => '0',
 827             RSTINMODE => '0',
 828             RSTM => '0',
 829             RSTP => '0'
 830             );
 831
 832     -- mask is 0 for 32-bit ops, 0x0000ffffffff for 64-bit
 833     p0_mask(47 downto 31) <= (others => '0');
 834     p0_mask(30 downto 0) <= (others => not r32_1);
 835
 836     p0: DSP48E1
 837         generic map (
 838             ACASCREG => 1,
 839             ALUMODEREG => 1,
 840             AREG => 1,
 841             BCASCREG => 1,
 842             BREG => 1,
 843             CARRYINREG => 0,
 844             CARRYINSELREG => 0,
 845             CREG => 1,
 846             INMODEREG => 0,
 847             MREG => 0,
 848             OPMODEREG => 0,
 849             PREG => 0,
 850             SEL_MASK => "C",
 851             USE_MULT => "none",
 852             USE_PATTERN_DETECT => "PATDET"
 853             )
 854         port map (
 855             A => m21_p(22 downto 0) & m03_p(5 downto 0) & '0',
 856             ACIN => (others => '0'),
 857             ALUMODE => "00" & rnot_1 & '0',
 858             B => (others => '0'),
 859             BCIN => (others => '0'),
 860             C => p0_mask,
 861             CARRYCASCIN => '0',
 862             CARRYIN => '0',
 863             CARRYINSEL => "000",
 864             CARRYOUT => p0_carry,
 865             CEA1 => '0',
 866             CEA2 => valid_1,
 867             CEAD => '0',
 868             CEALUMODE => valid_1,
 869             CEB1 => '0',
 870             CEB2 => valid_1,
 871             CEC => valid_1,
 872             CECARRYIN => '0',
 873             CECTRL => '0',
 874             CED => '0',
 875             CEINMODE => '0',
 876             CEM => '0',
 877             CEP => '0',
 878             CLK => clk,
 879             D => (others => '0'),
 880             INMODE => "00000",
 881             MULTSIGNIN => '0',
 882             OPMODE => "0010011",
 883             P => product(79 downto 32),
 884             PATTERNDETECT => p0_pat,
 885             PATTERNBDETECT => p0_patb,
 886             PCIN => s0_pc,
 887             RSTA => '0',
 888             RSTALLCARRYIN => '0',
 889             RSTALUMODE => '0',
 890             RSTB => '0',
 891             RSTC => '0',
 892             RSTCTRL => '0',
 893             RSTD => '0',
 894             RSTINMODE => '0',
 895             RSTM => '0',
 896             RSTP => '0'
 897             );
 898
 899     p1: DSP48E1
 900         generic map (
 901             ACASCREG => 1,
 902             ALUMODEREG => 1,
 903             AREG => 1,
 904             BCASCREG => 1,
 905             BREG => 1,
 906             CARRYINREG => 0,
 907             CARRYINSELREG => 0,
 908             CREG => 0,
 909             INMODEREG => 0,
 910             MASK => x"000000000000",
 911             MREG => 0,
 912             OPMODEREG => 0,
 913             PREG => 0,
 914             USE_MULT => "none",
 915             USE_PATTERN_DETECT => "PATDET"
 916             )
 917         port map (
 918             A => x"0000000" & '0' & m21_p(41),
 919             ACIN => (others => '0'),
 920             ALUMODE => "00" & rnot_1 & '0',
 921             B => m21_p(40 downto 23),
 922             BCIN => (others => '0'),
 923             C => (others => '0'),
 924             CARRYCASCIN => '0',
 925             CARRYIN => p0_carry(3),
 926             CARRYINSEL => "000",
 927             CEA1 => '0',
 928             CEA2 => valid_1,
 929             CEAD => '0',
 930             CEALUMODE => valid_1,
 931             CEB1 => '0',
 932             CEB2 => valid_1,
 933             CEC => '0',
 934             CECARRYIN => '0',
 935             CECTRL => '0',
 936             CED => '0',
 937             CEINMODE => '0',
 938             CEM => '0',
 939             CEP => '0',
 940             CLK => clk,
 941             D => (others => '0'),
 942             INMODE => "00000",
 943             MULTSIGNIN => '0',
 944             OPMODE => "0010011",
 945             P => product(127 downto 80),
 946             PATTERNDETECT => p1_pat,
 947             PATTERNBDETECT => p1_patb,
 948             PCIN => s1_pc,
 949             RSTA => '0',
 950             RSTALLCARRYIN => '0',
 951             RSTALUMODE => '0',
 952             RSTB => '0',
 953             RSTC => '0',
 954             RSTCTRL => '0',
 955             RSTD => '0',
 956             RSTINMODE => '0',
 957             RSTM => '0',
 958             RSTP => '0'
 959             );
 960
 961     mult_out: process(all)
 962         variable ov : std_ulogic;
 963     begin
 964         -- set overflow if the high bits are neither all zeroes nor all ones
 965         if req_32bit = '0' then
 966             ov := not ((p1_pat and p0_pat) or (p1_patb and p0_patb));
 967         else
 968             ov := not ((p1_pat and p0_pat and not product(31)) or
 969                        (p1_patb and p0_patb and product(31)));
 970         end if;
 971         ovf_in <= ov;
 972
 973         m_out.result <= product;
 974         m_out.overflow <= overflow;
 975     end process;
 976
 977     process(clk)
 978     begin
 979         if rising_edge(clk) then
 980             if rnot_1 = '0' then
 981                 product(31 downto 0) <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
 982             else
 983                 product(31 downto 0) <= not (m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0));
 984             end if;
 985             m_out.valid <= valid_1;
 986             valid_1 <= m_in.valid;
 987             req_32bit <= r32_1;
 988             r32_1 <= m_in.is_32bit;
 989             rnot_1 <= m_in.not_result;
 990             overflow <= ovf_in;
 991         end if;
 992     end process;
 993
 994 end architecture behaviour;
 995
 996 library ieee;
 997 use ieee.std_logic_1164.all;
 998 use ieee.numeric_std.all;
 999
1000 library unisim;
1001 use unisim.vcomponents.all;
1002
1003 entity short_multiply is
1004     port (
1005         clk   : in std_logic;
1006
1007         a_in  : in std_ulogic_vector(15 downto 0);
1008         b_in  : in std_ulogic_vector(15 downto 0);
1009         m_out : out std_ulogic_vector(31 downto 0)
1010         );
1011 end entity short_multiply;
1012
1013 architecture behaviour of short_multiply is
1014     signal mshort_p : std_ulogic_vector(47 downto 0);
1015 begin
1016     mshort: DSP48E1
1017         generic map (
1018             ACASCREG => 0,
1019             ALUMODEREG => 0,
1020             AREG => 0,
1021             BCASCREG => 0,
1022             BREG => 0,
1023             CARRYINREG => 0,
1024             CARRYINSELREG => 0,
1025             CREG => 0,
1026             INMODEREG => 0,
1027             MREG => 0,
1028             OPMODEREG => 0,
1029             PREG => 0
1030             )
1031         port map (
1032             A => std_ulogic_vector(resize(signed(a_in(15 downto 0)), 30)),
1033             ACIN => (others => '0'),
1034             ALUMODE => "0000",
1035             B => std_ulogic_vector(resize(signed(b_in(15 downto 0)), 18)),
1036             BCIN => (others => '0'),
1037             C => 48x"0",
1038             CARRYCASCIN => '0',
1039             CARRYIN => '0',
1040             CARRYINSEL => "000",
1041             CEA1 => '0',
1042             CEA2 => '0',
1043             CEAD => '0',
1044             CEALUMODE => '0',
1045             CEB1 => '0',
1046             CEB2 => '0',
1047             CEC => '0',
1048             CECARRYIN => '0',
1049             CECTRL => '0',
1050             CED => '0',
1051             CEINMODE => '0',
1052             CEM => '0',
1053             CEP => '0',
1054             CLK => clk,
1055             D => (others => '0'),
1056             INMODE => "00000",
1057             MULTSIGNIN => '0',
1058             OPMODE => "0110101",
1059             P => mshort_p,
1060             PCIN => (others => '0'),
1061             RSTA => '0',
1062             RSTALLCARRYIN => '0',
1063             RSTALUMODE => '0',
1064             RSTB => '0',
1065             RSTC => '0',
1066             RSTCTRL => '0',
1067             RSTD => '0',
1068             RSTINMODE => '0',
1069             RSTM => '0',
1070             RSTP => '0'
1071             );
1072
1073     m_out <= mshort_p(31 downto 0);
1074
1075 end architecture behaviour;