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Subject: Re: [libre-riscv-dev] minimum viable ASIC
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Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:50 [+0100]:
>=20
> * a PLL (this is quite a lot however it turns the ASIC from a 24mhz
> design into a 300mhz design)

Why only 24MHz without PLL ? You should have problems getting external
clock frequencies up to 100MHz without a problem inside a chip.


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