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Date: Thu, 26 Mar 2020 14:56:30 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Specification
X-Bugzilla-Version: unspecified
X-Bugzilla-Keywords: 
X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: mtnolan2640@gmail.com
X-Bugzilla-Status: CONFIRMED
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Message-ID: <bug-186-13-AdIEeSzgbb@http.bugs.libre-riscv.org/>
In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
References: <bug-186-13@http.bugs.libre-riscv.org/>
X-Bugzilla-URL: http://bugs.libre-riscv.org/
Auto-Submitted: auto-generated
MIME-Version: 1.0
Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
 RISC-V
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