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Date: Fri, 08 May 2020 14:37:52 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Source Code
X-Bugzilla-Version: unspecified
X-Bugzilla-Keywords: 
X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: yimmanuel3@gatech.edu
X-Bugzilla-Status: CONFIRMED
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X-Bugzilla-Priority: ---
X-Bugzilla-Assigned-To: lkcl@lkcl.net
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Message-ID: <bug-304-13-xAermu8zlP@https.bugs.libre-soc.org/>
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References: <bug-304-13@https.bugs.libre-soc.org/>
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Auto-Submitted: auto-generated
MIME-Version: 1.0
Subject: [libre-riscv-dev] [Bug 304] Define minimum viable interface set for
 180nm ASIC
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