# Crypto-router ASIC

* NLnet page: [[nlnet_2021_crypto_router]]
* Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>

# Specifications:

All of these are entirely Libre-Licensed:

* 300 mhz single-core,
  [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
  OpenPOWER CPU with
  [[openpower/sv/bitmanip]] extensions
* 180/130 nm (TBD)
* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
* 2x USB [[shakti/m_class/ULPI]] PHYs
* Direct DMA interface (independent bulk transfer)
* [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
  GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
* On-board Dual-ported SRAM (for Packet Buffers)
* Opencores [[shakti/m_class/sdram]]
* Wishbone interfaces to all peripherals
* [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
  Interrupt Controller

# Example packet transfer:

* Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
* Packet is **directly** stored in internal (dual-ported SRAM) by
  the RGMII PHY itself
* Interrupt notification is sent to the processor (XICS)
* Processor inspects packet over Wishbone interface directly
  connected to 2nd SRAM port.
* Processor computes, based on decoding the ETH Frame, where the
  packet must be sent to (which other RGM-II port: e.g. Port 2)
* Processor initiates Memory-to-Memory DMA transfer
* DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
  from one on-board SRAM to the target on-board SRAM associated with Port 2.
* DMA Engine generates interrupt (XICS) to the CPU to say it is completed
* Processor notifies target RGM-II PHY to activate "send" of frame out
  through target RGM-II port 2.