attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm0.src1_c"
module \src1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 0 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 1 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 2 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm0.src2_c"
module \src2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 0 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 1 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 2 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm0.src3_c"
module \src3_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 0 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 1 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 2 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm0.dst1_c"
module \dst1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 0 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 1 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 2 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm0.dst2_c"
module \dst2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 0 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 1 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 2 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm0"
module \dm0
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c \src1_c
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c \src2_c
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c \src3_c
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c \dst1_c
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c \dst2_c
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111111111110
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111111111110
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111111111110
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111111111110
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111111111110
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm1.src1_c"
module \src1_c$1
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm1.src2_c"
module \src2_c$2
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm1.src3_c"
module \src3_c$3
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm1.dst1_c"
module \dst1_c$4
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm1.dst2_c"
module \dst2_c$5
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm1"
module \dm1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$1 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$2 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$3 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$4 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$5 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111111111101
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111111111101
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111111111101
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111111111101
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111111111101
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm2.src1_c"
module \src1_c$6
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm2.src2_c"
module \src2_c$7
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm2.src3_c"
module \src3_c$8
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm2.dst1_c"
module \dst1_c$9
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm2.dst2_c"
module \dst2_c$10
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm2"
module \dm2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$6 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$7 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$8 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$9 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$10 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111111111011
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111111111011
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111111111011
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111111111011
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111111111011
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm3.src1_c"
module \src1_c$11
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm3.src2_c"
module \src2_c$12
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm3.src3_c"
module \src3_c$13
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm3.dst1_c"
module \dst1_c$14
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm3.dst2_c"
module \dst2_c$15
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm3"
module \dm3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$11 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$12 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$13 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$14 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$15 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111111110111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111111110111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111111110111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111111110111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111111110111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm4.src1_c"
module \src1_c$16
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm4.src2_c"
module \src2_c$17
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm4.src3_c"
module \src3_c$18
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm4.dst1_c"
module \dst1_c$19
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm4.dst2_c"
module \dst2_c$20
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm4"
module \dm4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$16 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$17 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$18 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$19 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$20 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111111101111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111111101111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111111101111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111111101111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111111101111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm5.src1_c"
module \src1_c$21
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm5.src2_c"
module \src2_c$22
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm5.src3_c"
module \src3_c$23
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm5.dst1_c"
module \dst1_c$24
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm5.dst2_c"
module \dst2_c$25
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm5"
module \dm5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$21 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$22 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$23 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$24 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$25 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111111011111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111111011111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111111011111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111111011111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111111011111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm6.src1_c"
module \src1_c$26
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm6.src2_c"
module \src2_c$27
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm6.src3_c"
module \src3_c$28
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm6.dst1_c"
module \dst1_c$29
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm6.dst2_c"
module \dst2_c$30
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm6"
module \dm6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$26 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$27 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$28 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$29 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$30 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111110111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111110111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111110111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111110111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111110111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm7.src1_c"
module \src1_c$31
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm7.src2_c"
module \src2_c$32
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm7.src3_c"
module \src3_c$33
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm7.dst1_c"
module \dst1_c$34
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm7.dst2_c"
module \dst2_c$35
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm7"
module \dm7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$31 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$32 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$33 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$34 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$35 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111101111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111101111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111101111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111101111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111101111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm8.src1_c"
module \src1_c$36
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm8.src2_c"
module \src2_c$37
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm8.src3_c"
module \src3_c$38
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm8.dst1_c"
module \dst1_c$39
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm8.dst2_c"
module \dst2_c$40
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm8"
module \dm8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$36 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$37 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$38 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$39 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$40 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111111011111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111111011111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111111011111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111111011111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111111011111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm9.src1_c"
module \src1_c$41
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm9.src2_c"
module \src2_c$42
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm9.src3_c"
module \src3_c$43
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm9.dst1_c"
module \dst1_c$44
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm9.dst2_c"
module \dst2_c$45
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm9"
module \dm9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$41 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$42 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$43 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$44 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$45 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111110111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111110111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111110111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111110111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111110111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm10.src1_c"
module \src1_c$46
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm10.src2_c"
module \src2_c$47
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm10.src3_c"
module \src3_c$48
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm10.dst1_c"
module \dst1_c$49
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm10.dst2_c"
module \dst2_c$50
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm10"
module \dm10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$46 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$47 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$48 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$49 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$50 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111101111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111101111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111101111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111101111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111101111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm11.src1_c"
module \src1_c$51
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm11.src2_c"
module \src2_c$52
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm11.src3_c"
module \src3_c$53
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm11.dst1_c"
module \dst1_c$54
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm11.dst2_c"
module \dst2_c$55
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm11"
module \dm11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$51 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$52 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$53 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$54 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$55 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111111011111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111111011111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111111011111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111111011111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111111011111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm12.src1_c"
module \src1_c$56
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm12.src2_c"
module \src2_c$57
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm12.src3_c"
module \src3_c$58
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm12.dst1_c"
module \dst1_c$59
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm12.dst2_c"
module \dst2_c$60
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm12"
module \dm12
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$56 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$57 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$58 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$59 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$60 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111110111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111110111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111110111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111110111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111110111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm13.src1_c"
module \src1_c$61
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm13.src2_c"
module \src2_c$62
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm13.src3_c"
module \src3_c$63
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm13.dst1_c"
module \dst1_c$64
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm13.dst2_c"
module \dst2_c$65
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm13"
module \dm13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$61 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$62 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$63 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$64 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$65 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111101111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111101111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111101111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111101111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111101111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm14.src1_c"
module \src1_c$66
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm14.src2_c"
module \src2_c$67
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm14.src3_c"
module \src3_c$68
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm14.dst1_c"
module \dst1_c$69
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm14.dst2_c"
module \dst2_c$70
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm14"
module \dm14
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$66 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$67 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$68 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$69 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$70 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111111011111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111111011111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111111011111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111111011111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111111011111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm15.src1_c"
module \src1_c$71
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm15.src2_c"
module \src2_c$72
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm15.src3_c"
module \src3_c$73
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm15.dst1_c"
module \dst1_c$74
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm15.dst2_c"
module \dst2_c$75
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm15"
module \dm15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$71 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$72 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$73 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$74 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$75 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111110111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111110111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111110111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111110111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111110111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm16.src1_c"
module \src1_c$76
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm16.src2_c"
module \src2_c$77
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm16.src3_c"
module \src3_c$78
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm16.dst1_c"
module \dst1_c$79
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm16.dst2_c"
module \dst2_c$80
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm16"
module \dm16
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$76 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$77 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$78 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$79 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$80 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111101111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111101111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111101111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111101111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111101111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm17.src1_c"
module \src1_c$81
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm17.src2_c"
module \src2_c$82
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm17.src3_c"
module \src3_c$83
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm17.dst1_c"
module \dst1_c$84
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm17.dst2_c"
module \dst2_c$85
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm17"
module \dm17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$81 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$82 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$83 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$84 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$85 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111111011111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111111011111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111111011111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111111011111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111111011111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm18.src1_c"
module \src1_c$86
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm18.src2_c"
module \src2_c$87
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm18.src3_c"
module \src3_c$88
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm18.dst1_c"
module \dst1_c$89
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm18.dst2_c"
module \dst2_c$90
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm18"
module \dm18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$86 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$87 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$88 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$89 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$90 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111110111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111110111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111110111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111110111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111110111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm19.src1_c"
module \src1_c$91
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm19.src2_c"
module \src2_c$92
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm19.src3_c"
module \src3_c$93
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm19.dst1_c"
module \dst1_c$94
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm19.dst2_c"
module \dst2_c$95
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm19"
module \dm19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$91 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$92 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$93 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$94 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$95 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111101111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111101111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111101111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111101111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111101111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm20.src1_c"
module \src1_c$96
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm20.src2_c"
module \src2_c$97
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm20.src3_c"
module \src3_c$98
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm20.dst1_c"
module \dst1_c$99
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm20.dst2_c"
module \dst2_c$100
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm20"
module \dm20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$96 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$97 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$98 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$99 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$100 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111111011111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111111011111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111111011111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111111011111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111111011111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm21.src1_c"
module \src1_c$101
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm21.src2_c"
module \src2_c$102
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm21.src3_c"
module \src3_c$103
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm21.dst1_c"
module \dst1_c$104
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm21.dst2_c"
module \dst2_c$105
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm21"
module \dm21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$101 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$102 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$103 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$104 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$105 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111110111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111110111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111110111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111110111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111110111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm22.src1_c"
module \src1_c$106
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm22.src2_c"
module \src2_c$107
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm22.src3_c"
module \src3_c$108
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm22.dst1_c"
module \dst1_c$109
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm22.dst2_c"
module \dst2_c$110
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm22"
module \dm22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$106 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$107 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$108 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$109 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$110 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111101111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111101111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111101111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111101111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111101111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm23.src1_c"
module \src1_c$111
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm23.src2_c"
module \src2_c$112
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm23.src3_c"
module \src3_c$113
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm23.dst1_c"
module \dst1_c$114
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm23.dst2_c"
module \dst2_c$115
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm23"
module \dm23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$111 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$112 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$113 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$114 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$115 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111111011111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111111011111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111111011111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111111011111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111111011111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm24.src1_c"
module \src1_c$116
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm24.src2_c"
module \src2_c$117
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm24.src3_c"
module \src3_c$118
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm24.dst1_c"
module \dst1_c$119
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm24.dst2_c"
module \dst2_c$120
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm24"
module \dm24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$116 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$117 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$118 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$119 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$120 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111110111111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111110111111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111110111111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111110111111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111110111111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm25.src1_c"
module \src1_c$121
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm25.src2_c"
module \src2_c$122
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm25.src3_c"
module \src3_c$123
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm25.dst1_c"
module \dst1_c$124
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm25.dst2_c"
module \dst2_c$125
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm25"
module \dm25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$121 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$122 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$123 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$124 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$125 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111101111111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111101111111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111101111111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111101111111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111101111111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm26.src1_c"
module \src1_c$126
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm26.src2_c"
module \src2_c$127
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm26.src3_c"
module \src3_c$128
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm26.dst1_c"
module \dst1_c$129
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm26.dst2_c"
module \dst2_c$130
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm26"
module \dm26
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$126 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$127 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$128 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$129 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$130 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'111011111111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'111011111111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'111011111111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'111011111111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'111011111111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm27.src1_c"
module \src1_c$131
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm27.src2_c"
module \src2_c$132
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm27.src3_c"
module \src3_c$133
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm27.dst1_c"
module \dst1_c$134
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm27.dst2_c"
module \dst2_c$135
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm27"
module \dm27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$131 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$132 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$133 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$134 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$135 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'110111111111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'110111111111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'110111111111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'110111111111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'110111111111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm28.src1_c"
module \src1_c$136
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm28.src2_c"
module \src2_c$137
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm28.src3_c"
module \src3_c$138
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm28.dst1_c"
module \dst1_c$139
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm28.dst2_c"
module \dst2_c$140
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm28"
module \dm28
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$136 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$137 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$138 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$139 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$140 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'101111111111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'101111111111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'101111111111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'101111111111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'101111111111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm29.src1_c"
module \src1_c$141
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd0_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd0_c 30'000000000000000000000000000000
    assign \q_rd0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd0_c 30'000000000000000000000000000000
    assign \qn_rd0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd0_c 30'000000000000000000000000000000
    assign \qlq_rd0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm29.src2_c"
module \src2_c$142
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd1_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd1_c 30'000000000000000000000000000000
    assign \q_rd1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd1_c 30'000000000000000000000000000000
    assign \qn_rd1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd1_c 30'000000000000000000000000000000
    assign \qlq_rd1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm29.src3_c"
module \src3_c$143
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_rd2_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_rd2_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_rd2_c
    connect \Y $11
  end
  process $group_1
    assign \q_rd2_c 30'000000000000000000000000000000
    assign \q_rd2_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \Y $13
  end
  process $group_2
    assign \qn_rd2_c 30'000000000000000000000000000000
    assign \qn_rd2_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_rd2_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_rd2_c 30'000000000000000000000000000000
    assign \qlq_rd2_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm29.dst1_c"
module \dst1_c$144
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr0_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr0_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr0_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr0_c 30'000000000000000000000000000000
    assign \q_wr0_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr0_c 30'000000000000000000000000000000
    assign \qn_wr0_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr0_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr0_c 30'000000000000000000000000000000
    assign \qlq_wr0_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm29.dst2_c"
module \dst2_c$145
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 input 2 \r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 input 3 \s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 output 4 \qlq_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 30 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 30 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $3
    connect \B \s_wr1_c
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 30'000000000000000000000000000000
    end
    sync init
      update \q_int 30'000000000000000000000000000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 30 \q_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \r_wr1_c
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $9
    connect \B \s_wr1_c
    connect \Y $11
  end
  process $group_1
    assign \q_wr1_c 30'000000000000000000000000000000
    assign \q_wr1_c $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 30 \qn_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 30 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \Y $13
  end
  process $group_2
    assign \qn_wr1_c 30'000000000000000000000000000000
    assign \qn_wr1_c $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \q_wr1_c
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq_wr1_c 30'000000000000000000000000000000
    assign \qlq_wr1_c $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.dm29"
module \dm29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 output 0 \rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 output 1 \wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 input 3 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 4 \gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 5 \gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 input 6 \gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 7 \gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 input 8 \gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 input 9 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 input 10 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src1_c_r_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src1_c_s_rd0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src1_c_qlq_rd0_c
  cell \src1_c$141 \src1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd0_c \src1_c_r_rd0_c
    connect \s_rd0_c \src1_c_s_rd0_c
    connect \qlq_rd0_c \src1_c_qlq_rd0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src2_c_r_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src2_c_s_rd1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src2_c_qlq_rd1_c
  cell \src2_c$142 \src2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd1_c \src2_c_r_rd1_c
    connect \s_rd1_c \src2_c_s_rd1_c
    connect \qlq_rd1_c \src2_c_qlq_rd1_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \src3_c_r_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \src3_c_s_rd2_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \src3_c_qlq_rd2_c
  cell \src3_c$143 \src3_c
    connect \rst \rst
    connect \clk \clk
    connect \r_rd2_c \src3_c_r_rd2_c
    connect \s_rd2_c \src3_c_s_rd2_c
    connect \qlq_rd2_c \src3_c_qlq_rd2_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst1_c_r_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst1_c_s_wr0_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst1_c_qlq_wr0_c
  cell \dst1_c$144 \dst1_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr0_c \dst1_c_r_wr0_c
    connect \s_wr0_c \dst1_c_s_wr0_c
    connect \qlq_wr0_c \dst1_c_qlq_wr0_c
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 30 \dst2_c_r_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 30 \dst2_c_s_wr1_c
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 30 \dst2_c_qlq_wr1_c
  cell \dst2_c$145 \dst2_c
    connect \rst \rst
    connect \clk \clk
    connect \r_wr1_c \dst2_c_r_wr1_c
    connect \s_wr1_c \dst2_c_s_wr1_c
    connect \qlq_wr1_c \dst2_c_qlq_wr1_c
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr1_i
    connect \B \go_die_i
    connect \Y $1
  end
  process $group_0
    assign \dst1_c_r_wr0_c 30'111111111111111111111111111111
    assign \dst1_c_r_wr0_c $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $4
    connect \B 30'011111111111111111111111111111
    connect \Y $6
  end
  connect $3 $6
  process $group_1
    assign \dst1_c_s_wr0_c 30'000000000000000000000000000000
    assign \dst1_c_s_wr0_c $3 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  wire width 30 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61"
  cell $or $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gowr2_i
    connect \B \go_die_i
    connect \Y $8
  end
  process $group_2
    assign \dst2_c_r_wr1_c 30'111111111111111111111111111111
    assign \dst2_c_r_wr1_c $8
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 30 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \wr_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  wire width 31 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $11
    connect \B 30'011111111111111111111111111111
    connect \Y $13
  end
  connect $10 $13
  process $group_3
    assign \dst2_c_s_wr1_c 30'000000000000000000000000000000
    assign \dst2_c_s_wr1_c $10 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord1_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_4
    assign \src1_c_r_rd0_c 30'111111111111111111111111111111
    assign \src1_c_r_rd0_c $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $19
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $18
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $18
    connect \B 30'011111111111111111111111111111
    connect \Y $20
  end
  connect $17 $20
  process $group_5
    assign \src1_c_s_rd0_c 30'000000000000000000000000000000
    assign \src1_c_s_rd0_c $17 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $23
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord2_i
    connect \B \go_die_i
    connect \Y $22
  end
  process $group_6
    assign \src2_c_r_rd1_c 30'111111111111111111111111111111
    assign \src2_c_r_rd1_c $22
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $25
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $28
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $25
    connect \B 30'011111111111111111111111111111
    connect \Y $27
  end
  connect $24 $27
  process $group_7
    assign \src2_c_s_rd1_c 30'000000000000000000000000000000
    assign \src2_c_s_rd1_c $24 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  wire width 30 $29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66"
  cell $or $30
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \gord3_i
    connect \B \go_die_i
    connect \Y $29
  end
  process $group_8
    assign \src3_c_r_rd2_c 30'111111111111111111111111111111
    assign \src3_c_r_rd2_c $29
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $31
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 30 $32
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $33
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \B \rd_pend_i
    connect \Y $32
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  wire width 31 $34
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67"
  cell $and $35
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11111
    connect \A $32
    connect \B 30'011111111111111111111111111111
    connect \Y $34
  end
  connect $31 $34
  process $group_9
    assign \src3_c_s_rd2_c 30'000000000000000000000000000000
    assign \src3_c_s_rd2_c $31 [29:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $36
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $37
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \src1_c_qlq_rd0_c
    connect \B \src2_c_qlq_rd1_c
    connect \Y $36
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $38
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $or $39
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $36
    connect \B \src3_c_qlq_rd2_c
    connect \Y $38
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $40
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $not $41
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $40
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  wire width 30 $42
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74"
  cell $and $43
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $38
    connect \B $40
    connect \Y $42
  end
  process $group_10
    assign \rd_wait_o 30'000000000000000000000000000000
    assign \rd_wait_o $42
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $44
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $or $45
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \dst1_c_qlq_wr0_c
    connect \B \dst2_c_qlq_wr1_c
    connect \Y $44
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $46
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $not $47
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A \issue_i
    connect \Y $46
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  wire width 30 $48
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78"
  cell $and $49
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 5'11110
    parameter \Y_WIDTH 5'11110
    connect \A $44
    connect \B $46
    connect \Y $48
  end
  process $group_11
    assign \wr_wait_o 30'000000000000000000000000000000
    assign \wr_wait_o $48
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x0"
module \fur_x0
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x1"
module \fur_x1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x2"
module \fur_x2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x3"
module \fur_x3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x4"
module \fur_x4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x5"
module \fur_x5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x6"
module \fur_x6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x7"
module \fur_x7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x8"
module \fur_x8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x9"
module \fur_x9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x10"
module \fur_x10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x11"
module \fur_x11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x12"
module \fur_x12
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x13"
module \fur_x13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x14"
module \fur_x14
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x15"
module \fur_x15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x16"
module \fur_x16
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x17"
module \fur_x17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x18"
module \fur_x18
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x19"
module \fur_x19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x20"
module \fur_x20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x21"
module \fur_x21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x22"
module \fur_x22
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x23"
module \fur_x23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x24"
module \fur_x24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x25"
module \fur_x25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x26"
module \fur_x26
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x27"
module \fur_x27
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x28"
module \fur_x28
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fur_x29"
module \fur_x29
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 output 0 \readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 output 1 \writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 input 2 \rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 input 3 \wr_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \wr_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
  end
  process $group_0
    assign \readable_o 1'0
    assign \readable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 5'11110
    parameter \Y_WIDTH 1'1
    connect \A \rd_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
  end
  process $group_1
    assign \writable_o 1'0
    assign \writable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "test_fu_fu_matrix"
module \test_fu_fu_matrix
  attribute \src "scoremulti/fu_fu_matrix.py:23"
  wire width 30 input 0 \rd_pend_i
  attribute \src "scoremulti/fu_fu_matrix.py:24"
  wire width 30 input 1 \wr_pend_i
  attribute \src "scoremulti/fu_fu_matrix.py:25"
  wire width 30 input 2 \issue_i
  attribute \src "scoremulti/fu_fu_matrix.py:27"
  wire width 30 input 3 \go_die_i
  attribute \src "scoremulti/fu_fu_matrix.py:36"
  wire width 30 input 4 \gowr1_i
  attribute \src "scoremulti/fu_fu_matrix.py:36"
  wire width 30 input 5 \gowr2_i
  attribute \src "scoremulti/fu_fu_matrix.py:36"
  wire width 30 input 6 \gowr3_i
  attribute \src "scoremulti/fu_fu_matrix.py:32"
  wire width 30 input 7 \gord1_i
  attribute \src "scoremulti/fu_fu_matrix.py:32"
  wire width 30 input 8 \gord2_i
  attribute \src "scoremulti/fu_fu_matrix.py:32"
  wire width 30 input 9 \gord3_i
  attribute \src "scoremulti/fu_fu_matrix.py:42"
  wire width 30 output 10 \readable_o
  attribute \src "scoremulti/fu_fu_matrix.py:43"
  wire width 30 output 11 \writable_o
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 13 \rst
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm0_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm0_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm0_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm0_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm0_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm0_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm0_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm0_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm0_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm0_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm0_wr_pend_i
  cell \dm0 \dm0
    connect \rd_wait_o \dm0_rd_wait_o
    connect \wr_wait_o \dm0_wr_wait_o
    connect \issue_i \dm0_issue_i
    connect \go_die_i \dm0_go_die_i
    connect \gord1_i \dm0_gord1_i
    connect \gord2_i \dm0_gord2_i
    connect \gord3_i \dm0_gord3_i
    connect \gowr1_i \dm0_gowr1_i
    connect \gowr2_i \dm0_gowr2_i
    connect \rd_pend_i \dm0_rd_pend_i
    connect \wr_pend_i \dm0_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm1_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm1_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm1_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm1_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm1_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm1_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm1_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm1_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm1_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm1_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm1_wr_pend_i
  cell \dm1 \dm1
    connect \rd_wait_o \dm1_rd_wait_o
    connect \wr_wait_o \dm1_wr_wait_o
    connect \issue_i \dm1_issue_i
    connect \go_die_i \dm1_go_die_i
    connect \gord1_i \dm1_gord1_i
    connect \gord2_i \dm1_gord2_i
    connect \gord3_i \dm1_gord3_i
    connect \gowr1_i \dm1_gowr1_i
    connect \gowr2_i \dm1_gowr2_i
    connect \rd_pend_i \dm1_rd_pend_i
    connect \wr_pend_i \dm1_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm2_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm2_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm2_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm2_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm2_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm2_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm2_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm2_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm2_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm2_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm2_wr_pend_i
  cell \dm2 \dm2
    connect \rd_wait_o \dm2_rd_wait_o
    connect \wr_wait_o \dm2_wr_wait_o
    connect \issue_i \dm2_issue_i
    connect \go_die_i \dm2_go_die_i
    connect \gord1_i \dm2_gord1_i
    connect \gord2_i \dm2_gord2_i
    connect \gord3_i \dm2_gord3_i
    connect \gowr1_i \dm2_gowr1_i
    connect \gowr2_i \dm2_gowr2_i
    connect \rd_pend_i \dm2_rd_pend_i
    connect \wr_pend_i \dm2_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm3_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm3_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm3_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm3_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm3_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm3_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm3_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm3_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm3_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm3_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm3_wr_pend_i
  cell \dm3 \dm3
    connect \rd_wait_o \dm3_rd_wait_o
    connect \wr_wait_o \dm3_wr_wait_o
    connect \issue_i \dm3_issue_i
    connect \go_die_i \dm3_go_die_i
    connect \gord1_i \dm3_gord1_i
    connect \gord2_i \dm3_gord2_i
    connect \gord3_i \dm3_gord3_i
    connect \gowr1_i \dm3_gowr1_i
    connect \gowr2_i \dm3_gowr2_i
    connect \rd_pend_i \dm3_rd_pend_i
    connect \wr_pend_i \dm3_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm4_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm4_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm4_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm4_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm4_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm4_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm4_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm4_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm4_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm4_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm4_wr_pend_i
  cell \dm4 \dm4
    connect \rd_wait_o \dm4_rd_wait_o
    connect \wr_wait_o \dm4_wr_wait_o
    connect \issue_i \dm4_issue_i
    connect \go_die_i \dm4_go_die_i
    connect \gord1_i \dm4_gord1_i
    connect \gord2_i \dm4_gord2_i
    connect \gord3_i \dm4_gord3_i
    connect \gowr1_i \dm4_gowr1_i
    connect \gowr2_i \dm4_gowr2_i
    connect \rd_pend_i \dm4_rd_pend_i
    connect \wr_pend_i \dm4_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm5_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm5_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm5_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm5_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm5_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm5_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm5_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm5_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm5_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm5_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm5_wr_pend_i
  cell \dm5 \dm5
    connect \rd_wait_o \dm5_rd_wait_o
    connect \wr_wait_o \dm5_wr_wait_o
    connect \issue_i \dm5_issue_i
    connect \go_die_i \dm5_go_die_i
    connect \gord1_i \dm5_gord1_i
    connect \gord2_i \dm5_gord2_i
    connect \gord3_i \dm5_gord3_i
    connect \gowr1_i \dm5_gowr1_i
    connect \gowr2_i \dm5_gowr2_i
    connect \rd_pend_i \dm5_rd_pend_i
    connect \wr_pend_i \dm5_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm6_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm6_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm6_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm6_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm6_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm6_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm6_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm6_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm6_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm6_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm6_wr_pend_i
  cell \dm6 \dm6
    connect \rd_wait_o \dm6_rd_wait_o
    connect \wr_wait_o \dm6_wr_wait_o
    connect \issue_i \dm6_issue_i
    connect \go_die_i \dm6_go_die_i
    connect \gord1_i \dm6_gord1_i
    connect \gord2_i \dm6_gord2_i
    connect \gord3_i \dm6_gord3_i
    connect \gowr1_i \dm6_gowr1_i
    connect \gowr2_i \dm6_gowr2_i
    connect \rd_pend_i \dm6_rd_pend_i
    connect \wr_pend_i \dm6_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm7_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm7_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm7_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm7_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm7_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm7_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm7_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm7_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm7_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm7_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm7_wr_pend_i
  cell \dm7 \dm7
    connect \rd_wait_o \dm7_rd_wait_o
    connect \wr_wait_o \dm7_wr_wait_o
    connect \issue_i \dm7_issue_i
    connect \go_die_i \dm7_go_die_i
    connect \gord1_i \dm7_gord1_i
    connect \gord2_i \dm7_gord2_i
    connect \gord3_i \dm7_gord3_i
    connect \gowr1_i \dm7_gowr1_i
    connect \gowr2_i \dm7_gowr2_i
    connect \rd_pend_i \dm7_rd_pend_i
    connect \wr_pend_i \dm7_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm8_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm8_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm8_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm8_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm8_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm8_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm8_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm8_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm8_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm8_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm8_wr_pend_i
  cell \dm8 \dm8
    connect \rd_wait_o \dm8_rd_wait_o
    connect \wr_wait_o \dm8_wr_wait_o
    connect \issue_i \dm8_issue_i
    connect \go_die_i \dm8_go_die_i
    connect \gord1_i \dm8_gord1_i
    connect \gord2_i \dm8_gord2_i
    connect \gord3_i \dm8_gord3_i
    connect \gowr1_i \dm8_gowr1_i
    connect \gowr2_i \dm8_gowr2_i
    connect \rd_pend_i \dm8_rd_pend_i
    connect \wr_pend_i \dm8_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm9_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm9_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm9_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm9_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm9_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm9_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm9_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm9_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm9_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm9_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm9_wr_pend_i
  cell \dm9 \dm9
    connect \rd_wait_o \dm9_rd_wait_o
    connect \wr_wait_o \dm9_wr_wait_o
    connect \issue_i \dm9_issue_i
    connect \go_die_i \dm9_go_die_i
    connect \gord1_i \dm9_gord1_i
    connect \gord2_i \dm9_gord2_i
    connect \gord3_i \dm9_gord3_i
    connect \gowr1_i \dm9_gowr1_i
    connect \gowr2_i \dm9_gowr2_i
    connect \rd_pend_i \dm9_rd_pend_i
    connect \wr_pend_i \dm9_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm10_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm10_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm10_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm10_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm10_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm10_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm10_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm10_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm10_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm10_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm10_wr_pend_i
  cell \dm10 \dm10
    connect \rd_wait_o \dm10_rd_wait_o
    connect \wr_wait_o \dm10_wr_wait_o
    connect \issue_i \dm10_issue_i
    connect \go_die_i \dm10_go_die_i
    connect \gord1_i \dm10_gord1_i
    connect \gord2_i \dm10_gord2_i
    connect \gord3_i \dm10_gord3_i
    connect \gowr1_i \dm10_gowr1_i
    connect \gowr2_i \dm10_gowr2_i
    connect \rd_pend_i \dm10_rd_pend_i
    connect \wr_pend_i \dm10_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm11_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm11_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm11_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm11_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm11_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm11_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm11_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm11_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm11_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm11_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm11_wr_pend_i
  cell \dm11 \dm11
    connect \rd_wait_o \dm11_rd_wait_o
    connect \wr_wait_o \dm11_wr_wait_o
    connect \issue_i \dm11_issue_i
    connect \go_die_i \dm11_go_die_i
    connect \gord1_i \dm11_gord1_i
    connect \gord2_i \dm11_gord2_i
    connect \gord3_i \dm11_gord3_i
    connect \gowr1_i \dm11_gowr1_i
    connect \gowr2_i \dm11_gowr2_i
    connect \rd_pend_i \dm11_rd_pend_i
    connect \wr_pend_i \dm11_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm12_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm12_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm12_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm12_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm12_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm12_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm12_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm12_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm12_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm12_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm12_wr_pend_i
  cell \dm12 \dm12
    connect \rd_wait_o \dm12_rd_wait_o
    connect \wr_wait_o \dm12_wr_wait_o
    connect \issue_i \dm12_issue_i
    connect \go_die_i \dm12_go_die_i
    connect \gord1_i \dm12_gord1_i
    connect \gord2_i \dm12_gord2_i
    connect \gord3_i \dm12_gord3_i
    connect \gowr1_i \dm12_gowr1_i
    connect \gowr2_i \dm12_gowr2_i
    connect \rd_pend_i \dm12_rd_pend_i
    connect \wr_pend_i \dm12_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm13_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm13_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm13_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm13_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm13_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm13_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm13_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm13_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm13_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm13_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm13_wr_pend_i
  cell \dm13 \dm13
    connect \rd_wait_o \dm13_rd_wait_o
    connect \wr_wait_o \dm13_wr_wait_o
    connect \issue_i \dm13_issue_i
    connect \go_die_i \dm13_go_die_i
    connect \gord1_i \dm13_gord1_i
    connect \gord2_i \dm13_gord2_i
    connect \gord3_i \dm13_gord3_i
    connect \gowr1_i \dm13_gowr1_i
    connect \gowr2_i \dm13_gowr2_i
    connect \rd_pend_i \dm13_rd_pend_i
    connect \wr_pend_i \dm13_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm14_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm14_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm14_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm14_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm14_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm14_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm14_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm14_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm14_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm14_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm14_wr_pend_i
  cell \dm14 \dm14
    connect \rd_wait_o \dm14_rd_wait_o
    connect \wr_wait_o \dm14_wr_wait_o
    connect \issue_i \dm14_issue_i
    connect \go_die_i \dm14_go_die_i
    connect \gord1_i \dm14_gord1_i
    connect \gord2_i \dm14_gord2_i
    connect \gord3_i \dm14_gord3_i
    connect \gowr1_i \dm14_gowr1_i
    connect \gowr2_i \dm14_gowr2_i
    connect \rd_pend_i \dm14_rd_pend_i
    connect \wr_pend_i \dm14_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm15_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm15_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm15_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm15_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm15_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm15_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm15_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm15_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm15_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm15_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm15_wr_pend_i
  cell \dm15 \dm15
    connect \rd_wait_o \dm15_rd_wait_o
    connect \wr_wait_o \dm15_wr_wait_o
    connect \issue_i \dm15_issue_i
    connect \go_die_i \dm15_go_die_i
    connect \gord1_i \dm15_gord1_i
    connect \gord2_i \dm15_gord2_i
    connect \gord3_i \dm15_gord3_i
    connect \gowr1_i \dm15_gowr1_i
    connect \gowr2_i \dm15_gowr2_i
    connect \rd_pend_i \dm15_rd_pend_i
    connect \wr_pend_i \dm15_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm16_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm16_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm16_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm16_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm16_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm16_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm16_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm16_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm16_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm16_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm16_wr_pend_i
  cell \dm16 \dm16
    connect \rd_wait_o \dm16_rd_wait_o
    connect \wr_wait_o \dm16_wr_wait_o
    connect \issue_i \dm16_issue_i
    connect \go_die_i \dm16_go_die_i
    connect \gord1_i \dm16_gord1_i
    connect \gord2_i \dm16_gord2_i
    connect \gord3_i \dm16_gord3_i
    connect \gowr1_i \dm16_gowr1_i
    connect \gowr2_i \dm16_gowr2_i
    connect \rd_pend_i \dm16_rd_pend_i
    connect \wr_pend_i \dm16_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm17_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm17_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm17_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm17_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm17_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm17_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm17_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm17_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm17_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm17_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm17_wr_pend_i
  cell \dm17 \dm17
    connect \rd_wait_o \dm17_rd_wait_o
    connect \wr_wait_o \dm17_wr_wait_o
    connect \issue_i \dm17_issue_i
    connect \go_die_i \dm17_go_die_i
    connect \gord1_i \dm17_gord1_i
    connect \gord2_i \dm17_gord2_i
    connect \gord3_i \dm17_gord3_i
    connect \gowr1_i \dm17_gowr1_i
    connect \gowr2_i \dm17_gowr2_i
    connect \rd_pend_i \dm17_rd_pend_i
    connect \wr_pend_i \dm17_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm18_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm18_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm18_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm18_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm18_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm18_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm18_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm18_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm18_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm18_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm18_wr_pend_i
  cell \dm18 \dm18
    connect \rd_wait_o \dm18_rd_wait_o
    connect \wr_wait_o \dm18_wr_wait_o
    connect \issue_i \dm18_issue_i
    connect \go_die_i \dm18_go_die_i
    connect \gord1_i \dm18_gord1_i
    connect \gord2_i \dm18_gord2_i
    connect \gord3_i \dm18_gord3_i
    connect \gowr1_i \dm18_gowr1_i
    connect \gowr2_i \dm18_gowr2_i
    connect \rd_pend_i \dm18_rd_pend_i
    connect \wr_pend_i \dm18_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm19_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm19_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm19_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm19_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm19_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm19_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm19_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm19_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm19_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm19_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm19_wr_pend_i
  cell \dm19 \dm19
    connect \rd_wait_o \dm19_rd_wait_o
    connect \wr_wait_o \dm19_wr_wait_o
    connect \issue_i \dm19_issue_i
    connect \go_die_i \dm19_go_die_i
    connect \gord1_i \dm19_gord1_i
    connect \gord2_i \dm19_gord2_i
    connect \gord3_i \dm19_gord3_i
    connect \gowr1_i \dm19_gowr1_i
    connect \gowr2_i \dm19_gowr2_i
    connect \rd_pend_i \dm19_rd_pend_i
    connect \wr_pend_i \dm19_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm20_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm20_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm20_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm20_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm20_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm20_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm20_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm20_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm20_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm20_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm20_wr_pend_i
  cell \dm20 \dm20
    connect \rd_wait_o \dm20_rd_wait_o
    connect \wr_wait_o \dm20_wr_wait_o
    connect \issue_i \dm20_issue_i
    connect \go_die_i \dm20_go_die_i
    connect \gord1_i \dm20_gord1_i
    connect \gord2_i \dm20_gord2_i
    connect \gord3_i \dm20_gord3_i
    connect \gowr1_i \dm20_gowr1_i
    connect \gowr2_i \dm20_gowr2_i
    connect \rd_pend_i \dm20_rd_pend_i
    connect \wr_pend_i \dm20_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm21_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm21_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm21_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm21_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm21_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm21_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm21_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm21_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm21_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm21_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm21_wr_pend_i
  cell \dm21 \dm21
    connect \rd_wait_o \dm21_rd_wait_o
    connect \wr_wait_o \dm21_wr_wait_o
    connect \issue_i \dm21_issue_i
    connect \go_die_i \dm21_go_die_i
    connect \gord1_i \dm21_gord1_i
    connect \gord2_i \dm21_gord2_i
    connect \gord3_i \dm21_gord3_i
    connect \gowr1_i \dm21_gowr1_i
    connect \gowr2_i \dm21_gowr2_i
    connect \rd_pend_i \dm21_rd_pend_i
    connect \wr_pend_i \dm21_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm22_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm22_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm22_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm22_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm22_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm22_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm22_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm22_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm22_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm22_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm22_wr_pend_i
  cell \dm22 \dm22
    connect \rd_wait_o \dm22_rd_wait_o
    connect \wr_wait_o \dm22_wr_wait_o
    connect \issue_i \dm22_issue_i
    connect \go_die_i \dm22_go_die_i
    connect \gord1_i \dm22_gord1_i
    connect \gord2_i \dm22_gord2_i
    connect \gord3_i \dm22_gord3_i
    connect \gowr1_i \dm22_gowr1_i
    connect \gowr2_i \dm22_gowr2_i
    connect \rd_pend_i \dm22_rd_pend_i
    connect \wr_pend_i \dm22_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm23_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm23_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm23_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm23_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm23_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm23_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm23_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm23_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm23_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm23_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm23_wr_pend_i
  cell \dm23 \dm23
    connect \rd_wait_o \dm23_rd_wait_o
    connect \wr_wait_o \dm23_wr_wait_o
    connect \issue_i \dm23_issue_i
    connect \go_die_i \dm23_go_die_i
    connect \gord1_i \dm23_gord1_i
    connect \gord2_i \dm23_gord2_i
    connect \gord3_i \dm23_gord3_i
    connect \gowr1_i \dm23_gowr1_i
    connect \gowr2_i \dm23_gowr2_i
    connect \rd_pend_i \dm23_rd_pend_i
    connect \wr_pend_i \dm23_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm24_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm24_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm24_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm24_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm24_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm24_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm24_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm24_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm24_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm24_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm24_wr_pend_i
  cell \dm24 \dm24
    connect \rd_wait_o \dm24_rd_wait_o
    connect \wr_wait_o \dm24_wr_wait_o
    connect \issue_i \dm24_issue_i
    connect \go_die_i \dm24_go_die_i
    connect \gord1_i \dm24_gord1_i
    connect \gord2_i \dm24_gord2_i
    connect \gord3_i \dm24_gord3_i
    connect \gowr1_i \dm24_gowr1_i
    connect \gowr2_i \dm24_gowr2_i
    connect \rd_pend_i \dm24_rd_pend_i
    connect \wr_pend_i \dm24_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm25_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm25_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm25_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm25_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm25_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm25_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm25_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm25_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm25_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm25_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm25_wr_pend_i
  cell \dm25 \dm25
    connect \rd_wait_o \dm25_rd_wait_o
    connect \wr_wait_o \dm25_wr_wait_o
    connect \issue_i \dm25_issue_i
    connect \go_die_i \dm25_go_die_i
    connect \gord1_i \dm25_gord1_i
    connect \gord2_i \dm25_gord2_i
    connect \gord3_i \dm25_gord3_i
    connect \gowr1_i \dm25_gowr1_i
    connect \gowr2_i \dm25_gowr2_i
    connect \rd_pend_i \dm25_rd_pend_i
    connect \wr_pend_i \dm25_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm26_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm26_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm26_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm26_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm26_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm26_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm26_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm26_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm26_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm26_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm26_wr_pend_i
  cell \dm26 \dm26
    connect \rd_wait_o \dm26_rd_wait_o
    connect \wr_wait_o \dm26_wr_wait_o
    connect \issue_i \dm26_issue_i
    connect \go_die_i \dm26_go_die_i
    connect \gord1_i \dm26_gord1_i
    connect \gord2_i \dm26_gord2_i
    connect \gord3_i \dm26_gord3_i
    connect \gowr1_i \dm26_gowr1_i
    connect \gowr2_i \dm26_gowr2_i
    connect \rd_pend_i \dm26_rd_pend_i
    connect \wr_pend_i \dm26_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm27_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm27_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm27_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm27_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm27_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm27_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm27_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm27_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm27_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm27_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm27_wr_pend_i
  cell \dm27 \dm27
    connect \rd_wait_o \dm27_rd_wait_o
    connect \wr_wait_o \dm27_wr_wait_o
    connect \issue_i \dm27_issue_i
    connect \go_die_i \dm27_go_die_i
    connect \gord1_i \dm27_gord1_i
    connect \gord2_i \dm27_gord2_i
    connect \gord3_i \dm27_gord3_i
    connect \gowr1_i \dm27_gowr1_i
    connect \gowr2_i \dm27_gowr2_i
    connect \rd_pend_i \dm27_rd_pend_i
    connect \wr_pend_i \dm27_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm28_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm28_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm28_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm28_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm28_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm28_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm28_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm28_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm28_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm28_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm28_wr_pend_i
  cell \dm28 \dm28
    connect \rd_wait_o \dm28_rd_wait_o
    connect \wr_wait_o \dm28_wr_wait_o
    connect \issue_i \dm28_issue_i
    connect \go_die_i \dm28_go_die_i
    connect \gord1_i \dm28_gord1_i
    connect \gord2_i \dm28_gord2_i
    connect \gord3_i \dm28_gord3_i
    connect \gowr1_i \dm28_gowr1_i
    connect \gowr2_i \dm28_gowr2_i
    connect \rd_pend_i \dm28_rd_pend_i
    connect \wr_pend_i \dm28_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39"
  wire width 30 \dm29_rd_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40"
  wire width 30 \dm29_wr_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21"
  wire width 30 \dm29_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36"
  wire width 30 \dm29_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm29_gord1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm29_gord2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27"
  wire width 30 \dm29_gord3_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm29_gowr1_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31"
  wire width 30 \dm29_gowr2_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19"
  wire width 30 \dm29_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20"
  wire width 30 \dm29_wr_pend_i
  cell \dm29 \dm29
    connect \rd_wait_o \dm29_rd_wait_o
    connect \wr_wait_o \dm29_wr_wait_o
    connect \issue_i \dm29_issue_i
    connect \go_die_i \dm29_go_die_i
    connect \gord1_i \dm29_gord1_i
    connect \gord2_i \dm29_gord2_i
    connect \gord3_i \dm29_gord3_i
    connect \gowr1_i \dm29_gowr1_i
    connect \gowr2_i \dm29_gowr2_i
    connect \rd_pend_i \dm29_rd_pend_i
    connect \wr_pend_i \dm29_wr_pend_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x0_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x0_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x0_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x0_wr_pend_i
  cell \fur_x0 \fur_x0
    connect \readable_o \fur_x0_readable_o
    connect \writable_o \fur_x0_writable_o
    connect \rd_pend_i \fur_x0_rd_pend_i
    connect \wr_pend_i \fur_x0_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x1_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x1_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x1_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x1_wr_pend_i
  cell \fur_x1 \fur_x1
    connect \readable_o \fur_x1_readable_o
    connect \writable_o \fur_x1_writable_o
    connect \rd_pend_i \fur_x1_rd_pend_i
    connect \wr_pend_i \fur_x1_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x2_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x2_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x2_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x2_wr_pend_i
  cell \fur_x2 \fur_x2
    connect \readable_o \fur_x2_readable_o
    connect \writable_o \fur_x2_writable_o
    connect \rd_pend_i \fur_x2_rd_pend_i
    connect \wr_pend_i \fur_x2_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x3_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x3_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x3_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x3_wr_pend_i
  cell \fur_x3 \fur_x3
    connect \readable_o \fur_x3_readable_o
    connect \writable_o \fur_x3_writable_o
    connect \rd_pend_i \fur_x3_rd_pend_i
    connect \wr_pend_i \fur_x3_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x4_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x4_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x4_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x4_wr_pend_i
  cell \fur_x4 \fur_x4
    connect \readable_o \fur_x4_readable_o
    connect \writable_o \fur_x4_writable_o
    connect \rd_pend_i \fur_x4_rd_pend_i
    connect \wr_pend_i \fur_x4_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x5_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x5_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x5_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x5_wr_pend_i
  cell \fur_x5 \fur_x5
    connect \readable_o \fur_x5_readable_o
    connect \writable_o \fur_x5_writable_o
    connect \rd_pend_i \fur_x5_rd_pend_i
    connect \wr_pend_i \fur_x5_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x6_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x6_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x6_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x6_wr_pend_i
  cell \fur_x6 \fur_x6
    connect \readable_o \fur_x6_readable_o
    connect \writable_o \fur_x6_writable_o
    connect \rd_pend_i \fur_x6_rd_pend_i
    connect \wr_pend_i \fur_x6_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x7_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x7_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x7_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x7_wr_pend_i
  cell \fur_x7 \fur_x7
    connect \readable_o \fur_x7_readable_o
    connect \writable_o \fur_x7_writable_o
    connect \rd_pend_i \fur_x7_rd_pend_i
    connect \wr_pend_i \fur_x7_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x8_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x8_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x8_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x8_wr_pend_i
  cell \fur_x8 \fur_x8
    connect \readable_o \fur_x8_readable_o
    connect \writable_o \fur_x8_writable_o
    connect \rd_pend_i \fur_x8_rd_pend_i
    connect \wr_pend_i \fur_x8_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x9_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x9_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x9_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x9_wr_pend_i
  cell \fur_x9 \fur_x9
    connect \readable_o \fur_x9_readable_o
    connect \writable_o \fur_x9_writable_o
    connect \rd_pend_i \fur_x9_rd_pend_i
    connect \wr_pend_i \fur_x9_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x10_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x10_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x10_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x10_wr_pend_i
  cell \fur_x10 \fur_x10
    connect \readable_o \fur_x10_readable_o
    connect \writable_o \fur_x10_writable_o
    connect \rd_pend_i \fur_x10_rd_pend_i
    connect \wr_pend_i \fur_x10_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x11_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x11_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x11_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x11_wr_pend_i
  cell \fur_x11 \fur_x11
    connect \readable_o \fur_x11_readable_o
    connect \writable_o \fur_x11_writable_o
    connect \rd_pend_i \fur_x11_rd_pend_i
    connect \wr_pend_i \fur_x11_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x12_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x12_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x12_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x12_wr_pend_i
  cell \fur_x12 \fur_x12
    connect \readable_o \fur_x12_readable_o
    connect \writable_o \fur_x12_writable_o
    connect \rd_pend_i \fur_x12_rd_pend_i
    connect \wr_pend_i \fur_x12_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x13_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x13_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x13_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x13_wr_pend_i
  cell \fur_x13 \fur_x13
    connect \readable_o \fur_x13_readable_o
    connect \writable_o \fur_x13_writable_o
    connect \rd_pend_i \fur_x13_rd_pend_i
    connect \wr_pend_i \fur_x13_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x14_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x14_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x14_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x14_wr_pend_i
  cell \fur_x14 \fur_x14
    connect \readable_o \fur_x14_readable_o
    connect \writable_o \fur_x14_writable_o
    connect \rd_pend_i \fur_x14_rd_pend_i
    connect \wr_pend_i \fur_x14_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x15_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x15_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x15_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x15_wr_pend_i
  cell \fur_x15 \fur_x15
    connect \readable_o \fur_x15_readable_o
    connect \writable_o \fur_x15_writable_o
    connect \rd_pend_i \fur_x15_rd_pend_i
    connect \wr_pend_i \fur_x15_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x16_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x16_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x16_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x16_wr_pend_i
  cell \fur_x16 \fur_x16
    connect \readable_o \fur_x16_readable_o
    connect \writable_o \fur_x16_writable_o
    connect \rd_pend_i \fur_x16_rd_pend_i
    connect \wr_pend_i \fur_x16_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x17_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x17_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x17_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x17_wr_pend_i
  cell \fur_x17 \fur_x17
    connect \readable_o \fur_x17_readable_o
    connect \writable_o \fur_x17_writable_o
    connect \rd_pend_i \fur_x17_rd_pend_i
    connect \wr_pend_i \fur_x17_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x18_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x18_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x18_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x18_wr_pend_i
  cell \fur_x18 \fur_x18
    connect \readable_o \fur_x18_readable_o
    connect \writable_o \fur_x18_writable_o
    connect \rd_pend_i \fur_x18_rd_pend_i
    connect \wr_pend_i \fur_x18_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x19_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x19_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x19_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x19_wr_pend_i
  cell \fur_x19 \fur_x19
    connect \readable_o \fur_x19_readable_o
    connect \writable_o \fur_x19_writable_o
    connect \rd_pend_i \fur_x19_rd_pend_i
    connect \wr_pend_i \fur_x19_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x20_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x20_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x20_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x20_wr_pend_i
  cell \fur_x20 \fur_x20
    connect \readable_o \fur_x20_readable_o
    connect \writable_o \fur_x20_writable_o
    connect \rd_pend_i \fur_x20_rd_pend_i
    connect \wr_pend_i \fur_x20_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x21_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x21_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x21_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x21_wr_pend_i
  cell \fur_x21 \fur_x21
    connect \readable_o \fur_x21_readable_o
    connect \writable_o \fur_x21_writable_o
    connect \rd_pend_i \fur_x21_rd_pend_i
    connect \wr_pend_i \fur_x21_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x22_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x22_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x22_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x22_wr_pend_i
  cell \fur_x22 \fur_x22
    connect \readable_o \fur_x22_readable_o
    connect \writable_o \fur_x22_writable_o
    connect \rd_pend_i \fur_x22_rd_pend_i
    connect \wr_pend_i \fur_x22_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x23_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x23_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x23_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x23_wr_pend_i
  cell \fur_x23 \fur_x23
    connect \readable_o \fur_x23_readable_o
    connect \writable_o \fur_x23_writable_o
    connect \rd_pend_i \fur_x23_rd_pend_i
    connect \wr_pend_i \fur_x23_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x24_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x24_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x24_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x24_wr_pend_i
  cell \fur_x24 \fur_x24
    connect \readable_o \fur_x24_readable_o
    connect \writable_o \fur_x24_writable_o
    connect \rd_pend_i \fur_x24_rd_pend_i
    connect \wr_pend_i \fur_x24_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x25_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x25_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x25_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x25_wr_pend_i
  cell \fur_x25 \fur_x25
    connect \readable_o \fur_x25_readable_o
    connect \writable_o \fur_x25_writable_o
    connect \rd_pend_i \fur_x25_rd_pend_i
    connect \wr_pend_i \fur_x25_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x26_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x26_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x26_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x26_wr_pend_i
  cell \fur_x26 \fur_x26
    connect \readable_o \fur_x26_readable_o
    connect \writable_o \fur_x26_writable_o
    connect \rd_pend_i \fur_x26_rd_pend_i
    connect \wr_pend_i \fur_x26_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x27_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x27_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x27_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x27_wr_pend_i
  cell \fur_x27 \fur_x27
    connect \readable_o \fur_x27_readable_o
    connect \writable_o \fur_x27_writable_o
    connect \rd_pend_i \fur_x27_rd_pend_i
    connect \wr_pend_i \fur_x27_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x28_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x28_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x28_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x28_wr_pend_i
  cell \fur_x28 \fur_x28
    connect \readable_o \fur_x28_readable_o
    connect \writable_o \fur_x28_writable_o
    connect \rd_pend_i \fur_x28_rd_pend_i
    connect \wr_pend_i \fur_x28_wr_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13"
  wire width 1 \fur_x29_readable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14"
  wire width 1 \fur_x29_writable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10"
  wire width 30 \fur_x29_rd_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11"
  wire width 30 \fur_x29_wr_pend_i
  cell \fur_x29 \fur_x29
    connect \readable_o \fur_x29_readable_o
    connect \writable_o \fur_x29_writable_o
    connect \rd_pend_i \fur_x29_rd_pend_i
    connect \wr_pend_i \fur_x29_wr_pend_i
  end
  process $group_0
    assign \readable_o 30'000000000000000000000000000000
    assign \readable_o { \fur_x29_readable_o \fur_x28_readable_o \fur_x27_readable_o \fur_x26_readable_o \fur_x25_readable_o \fur_x24_readable_o \fur_x23_readable_o \fur_x22_readable_o \fur_x21_readable_o \fur_x20_readable_o \fur_x19_readable_o \fur_x18_readable_o \fur_x17_readable_o \fur_x16_readable_o \fur_x15_readable_o \fur_x14_readable_o \fur_x13_readable_o \fur_x12_readable_o \fur_x11_readable_o \fur_x10_readable_o \fur_x9_readable_o \fur_x8_readable_o \fur_x7_readable_o \fur_x6_readable_o \fur_x5_readable_o \fur_x4_readable_o \fur_x3_readable_o \fur_x2_readable_o \fur_x1_readable_o \fur_x0_readable_o }
    sync init
  end
  process $group_1
    assign \writable_o 30'000000000000000000000000000000
    assign \writable_o { \fur_x29_writable_o \fur_x28_writable_o \fur_x27_writable_o \fur_x26_writable_o \fur_x25_writable_o \fur_x24_writable_o \fur_x23_writable_o \fur_x22_writable_o \fur_x21_writable_o \fur_x20_writable_o \fur_x19_writable_o \fur_x18_writable_o \fur_x17_writable_o \fur_x16_writable_o \fur_x15_writable_o \fur_x14_writable_o \fur_x13_writable_o \fur_x12_writable_o \fur_x11_writable_o \fur_x10_writable_o \fur_x9_writable_o \fur_x8_writable_o \fur_x7_writable_o \fur_x6_writable_o \fur_x5_writable_o \fur_x4_writable_o \fur_x3_writable_o \fur_x2_writable_o \fur_x1_writable_o \fur_x0_writable_o }
    sync init
  end
  process $group_2
    assign \fur_x0_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x0_rd_pend_i \dm0_rd_wait_o
    sync init
  end
  process $group_3
    assign \fur_x0_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x0_wr_pend_i \dm0_wr_wait_o
    sync init
  end
  process $group_4
    assign \fur_x1_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x1_rd_pend_i \dm1_rd_wait_o
    sync init
  end
  process $group_5
    assign \fur_x1_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x1_wr_pend_i \dm1_wr_wait_o
    sync init
  end
  process $group_6
    assign \fur_x2_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x2_rd_pend_i \dm2_rd_wait_o
    sync init
  end
  process $group_7
    assign \fur_x2_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x2_wr_pend_i \dm2_wr_wait_o
    sync init
  end
  process $group_8
    assign \fur_x3_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x3_rd_pend_i \dm3_rd_wait_o
    sync init
  end
  process $group_9
    assign \fur_x3_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x3_wr_pend_i \dm3_wr_wait_o
    sync init
  end
  process $group_10
    assign \fur_x4_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x4_rd_pend_i \dm4_rd_wait_o
    sync init
  end
  process $group_11
    assign \fur_x4_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x4_wr_pend_i \dm4_wr_wait_o
    sync init
  end
  process $group_12
    assign \fur_x5_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x5_rd_pend_i \dm5_rd_wait_o
    sync init
  end
  process $group_13
    assign \fur_x5_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x5_wr_pend_i \dm5_wr_wait_o
    sync init
  end
  process $group_14
    assign \fur_x6_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x6_rd_pend_i \dm6_rd_wait_o
    sync init
  end
  process $group_15
    assign \fur_x6_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x6_wr_pend_i \dm6_wr_wait_o
    sync init
  end
  process $group_16
    assign \fur_x7_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x7_rd_pend_i \dm7_rd_wait_o
    sync init
  end
  process $group_17
    assign \fur_x7_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x7_wr_pend_i \dm7_wr_wait_o
    sync init
  end
  process $group_18
    assign \fur_x8_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x8_rd_pend_i \dm8_rd_wait_o
    sync init
  end
  process $group_19
    assign \fur_x8_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x8_wr_pend_i \dm8_wr_wait_o
    sync init
  end
  process $group_20
    assign \fur_x9_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x9_rd_pend_i \dm9_rd_wait_o
    sync init
  end
  process $group_21
    assign \fur_x9_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x9_wr_pend_i \dm9_wr_wait_o
    sync init
  end
  process $group_22
    assign \fur_x10_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x10_rd_pend_i \dm10_rd_wait_o
    sync init
  end
  process $group_23
    assign \fur_x10_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x10_wr_pend_i \dm10_wr_wait_o
    sync init
  end
  process $group_24
    assign \fur_x11_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x11_rd_pend_i \dm11_rd_wait_o
    sync init
  end
  process $group_25
    assign \fur_x11_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x11_wr_pend_i \dm11_wr_wait_o
    sync init
  end
  process $group_26
    assign \fur_x12_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x12_rd_pend_i \dm12_rd_wait_o
    sync init
  end
  process $group_27
    assign \fur_x12_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x12_wr_pend_i \dm12_wr_wait_o
    sync init
  end
  process $group_28
    assign \fur_x13_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x13_rd_pend_i \dm13_rd_wait_o
    sync init
  end
  process $group_29
    assign \fur_x13_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x13_wr_pend_i \dm13_wr_wait_o
    sync init
  end
  process $group_30
    assign \fur_x14_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x14_rd_pend_i \dm14_rd_wait_o
    sync init
  end
  process $group_31
    assign \fur_x14_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x14_wr_pend_i \dm14_wr_wait_o
    sync init
  end
  process $group_32
    assign \fur_x15_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x15_rd_pend_i \dm15_rd_wait_o
    sync init
  end
  process $group_33
    assign \fur_x15_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x15_wr_pend_i \dm15_wr_wait_o
    sync init
  end
  process $group_34
    assign \fur_x16_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x16_rd_pend_i \dm16_rd_wait_o
    sync init
  end
  process $group_35
    assign \fur_x16_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x16_wr_pend_i \dm16_wr_wait_o
    sync init
  end
  process $group_36
    assign \fur_x17_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x17_rd_pend_i \dm17_rd_wait_o
    sync init
  end
  process $group_37
    assign \fur_x17_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x17_wr_pend_i \dm17_wr_wait_o
    sync init
  end
  process $group_38
    assign \fur_x18_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x18_rd_pend_i \dm18_rd_wait_o
    sync init
  end
  process $group_39
    assign \fur_x18_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x18_wr_pend_i \dm18_wr_wait_o
    sync init
  end
  process $group_40
    assign \fur_x19_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x19_rd_pend_i \dm19_rd_wait_o
    sync init
  end
  process $group_41
    assign \fur_x19_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x19_wr_pend_i \dm19_wr_wait_o
    sync init
  end
  process $group_42
    assign \fur_x20_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x20_rd_pend_i \dm20_rd_wait_o
    sync init
  end
  process $group_43
    assign \fur_x20_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x20_wr_pend_i \dm20_wr_wait_o
    sync init
  end
  process $group_44
    assign \fur_x21_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x21_rd_pend_i \dm21_rd_wait_o
    sync init
  end
  process $group_45
    assign \fur_x21_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x21_wr_pend_i \dm21_wr_wait_o
    sync init
  end
  process $group_46
    assign \fur_x22_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x22_rd_pend_i \dm22_rd_wait_o
    sync init
  end
  process $group_47
    assign \fur_x22_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x22_wr_pend_i \dm22_wr_wait_o
    sync init
  end
  process $group_48
    assign \fur_x23_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x23_rd_pend_i \dm23_rd_wait_o
    sync init
  end
  process $group_49
    assign \fur_x23_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x23_wr_pend_i \dm23_wr_wait_o
    sync init
  end
  process $group_50
    assign \fur_x24_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x24_rd_pend_i \dm24_rd_wait_o
    sync init
  end
  process $group_51
    assign \fur_x24_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x24_wr_pend_i \dm24_wr_wait_o
    sync init
  end
  process $group_52
    assign \fur_x25_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x25_rd_pend_i \dm25_rd_wait_o
    sync init
  end
  process $group_53
    assign \fur_x25_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x25_wr_pend_i \dm25_wr_wait_o
    sync init
  end
  process $group_54
    assign \fur_x26_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x26_rd_pend_i \dm26_rd_wait_o
    sync init
  end
  process $group_55
    assign \fur_x26_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x26_wr_pend_i \dm26_wr_wait_o
    sync init
  end
  process $group_56
    assign \fur_x27_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x27_rd_pend_i \dm27_rd_wait_o
    sync init
  end
  process $group_57
    assign \fur_x27_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x27_wr_pend_i \dm27_wr_wait_o
    sync init
  end
  process $group_58
    assign \fur_x28_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x28_rd_pend_i \dm28_rd_wait_o
    sync init
  end
  process $group_59
    assign \fur_x28_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x28_wr_pend_i \dm28_wr_wait_o
    sync init
  end
  process $group_60
    assign \fur_x29_rd_pend_i 30'000000000000000000000000000000
    assign \fur_x29_rd_pend_i \dm29_rd_wait_o
    sync init
  end
  process $group_61
    assign \fur_x29_wr_pend_i 30'000000000000000000000000000000
    assign \fur_x29_wr_pend_i \dm29_wr_wait_o
    sync init
  end
  process $group_62
    assign \dm0_issue_i 30'000000000000000000000000000000
    assign \dm1_issue_i 30'000000000000000000000000000000
    assign \dm2_issue_i 30'000000000000000000000000000000
    assign \dm3_issue_i 30'000000000000000000000000000000
    assign \dm4_issue_i 30'000000000000000000000000000000
    assign \dm5_issue_i 30'000000000000000000000000000000
    assign \dm6_issue_i 30'000000000000000000000000000000
    assign \dm7_issue_i 30'000000000000000000000000000000
    assign \dm8_issue_i 30'000000000000000000000000000000
    assign \dm9_issue_i 30'000000000000000000000000000000
    assign \dm10_issue_i 30'000000000000000000000000000000
    assign \dm11_issue_i 30'000000000000000000000000000000
    assign \dm12_issue_i 30'000000000000000000000000000000
    assign \dm13_issue_i 30'000000000000000000000000000000
    assign \dm14_issue_i 30'000000000000000000000000000000
    assign \dm15_issue_i 30'000000000000000000000000000000
    assign \dm16_issue_i 30'000000000000000000000000000000
    assign \dm17_issue_i 30'000000000000000000000000000000
    assign \dm18_issue_i 30'000000000000000000000000000000
    assign \dm19_issue_i 30'000000000000000000000000000000
    assign \dm20_issue_i 30'000000000000000000000000000000
    assign \dm21_issue_i 30'000000000000000000000000000000
    assign \dm22_issue_i 30'000000000000000000000000000000
    assign \dm23_issue_i 30'000000000000000000000000000000
    assign \dm24_issue_i 30'000000000000000000000000000000
    assign \dm25_issue_i 30'000000000000000000000000000000
    assign \dm26_issue_i 30'000000000000000000000000000000
    assign \dm27_issue_i 30'000000000000000000000000000000
    assign \dm28_issue_i 30'000000000000000000000000000000
    assign \dm29_issue_i 30'000000000000000000000000000000
    assign { \dm29_issue_i [0] \dm28_issue_i [0] \dm27_issue_i [0] \dm26_issue_i [0] \dm25_issue_i [0] \dm24_issue_i [0] \dm23_issue_i [0] \dm22_issue_i [0] \dm21_issue_i [0] \dm20_issue_i [0] \dm19_issue_i [0] \dm18_issue_i [0] \dm17_issue_i [0] \dm16_issue_i [0] \dm15_issue_i [0] \dm14_issue_i [0] \dm13_issue_i [0] \dm12_issue_i [0] \dm11_issue_i [0] \dm10_issue_i [0] \dm9_issue_i [0] \dm8_issue_i [0] \dm7_issue_i [0] \dm6_issue_i [0] \dm5_issue_i [0] \dm4_issue_i [0] \dm3_issue_i [0] \dm2_issue_i [0] \dm1_issue_i [0] \dm0_issue_i [0] } \issue_i
    assign { \dm29_issue_i [1] \dm28_issue_i [1] \dm27_issue_i [1] \dm26_issue_i [1] \dm25_issue_i [1] \dm24_issue_i [1] \dm23_issue_i [1] \dm22_issue_i [1] \dm21_issue_i [1] \dm20_issue_i [1] \dm19_issue_i [1] \dm18_issue_i [1] \dm17_issue_i [1] \dm16_issue_i [1] \dm15_issue_i [1] \dm14_issue_i [1] \dm13_issue_i [1] \dm12_issue_i [1] \dm11_issue_i [1] \dm10_issue_i [1] \dm9_issue_i [1] \dm8_issue_i [1] \dm7_issue_i [1] \dm6_issue_i [1] \dm5_issue_i [1] \dm4_issue_i [1] \dm3_issue_i [1] \dm2_issue_i [1] \dm1_issue_i [1] \dm0_issue_i [1] } \issue_i
    assign { \dm29_issue_i [2] \dm28_issue_i [2] \dm27_issue_i [2] \dm26_issue_i [2] \dm25_issue_i [2] \dm24_issue_i [2] \dm23_issue_i [2] \dm22_issue_i [2] \dm21_issue_i [2] \dm20_issue_i [2] \dm19_issue_i [2] \dm18_issue_i [2] \dm17_issue_i [2] \dm16_issue_i [2] \dm15_issue_i [2] \dm14_issue_i [2] \dm13_issue_i [2] \dm12_issue_i [2] \dm11_issue_i [2] \dm10_issue_i [2] \dm9_issue_i [2] \dm8_issue_i [2] \dm7_issue_i [2] \dm6_issue_i [2] \dm5_issue_i [2] \dm4_issue_i [2] \dm3_issue_i [2] \dm2_issue_i [2] \dm1_issue_i [2] \dm0_issue_i [2] } \issue_i
    assign { \dm29_issue_i [3] \dm28_issue_i [3] \dm27_issue_i [3] \dm26_issue_i [3] \dm25_issue_i [3] \dm24_issue_i [3] \dm23_issue_i [3] \dm22_issue_i [3] \dm21_issue_i [3] \dm20_issue_i [3] \dm19_issue_i [3] \dm18_issue_i [3] \dm17_issue_i [3] \dm16_issue_i [3] \dm15_issue_i [3] \dm14_issue_i [3] \dm13_issue_i [3] \dm12_issue_i [3] \dm11_issue_i [3] \dm10_issue_i [3] \dm9_issue_i [3] \dm8_issue_i [3] \dm7_issue_i [3] \dm6_issue_i [3] \dm5_issue_i [3] \dm4_issue_i [3] \dm3_issue_i [3] \dm2_issue_i [3] \dm1_issue_i [3] \dm0_issue_i [3] } \issue_i
    assign { \dm29_issue_i [4] \dm28_issue_i [4] \dm27_issue_i [4] \dm26_issue_i [4] \dm25_issue_i [4] \dm24_issue_i [4] \dm23_issue_i [4] \dm22_issue_i [4] \dm21_issue_i [4] \dm20_issue_i [4] \dm19_issue_i [4] \dm18_issue_i [4] \dm17_issue_i [4] \dm16_issue_i [4] \dm15_issue_i [4] \dm14_issue_i [4] \dm13_issue_i [4] \dm12_issue_i [4] \dm11_issue_i [4] \dm10_issue_i [4] \dm9_issue_i [4] \dm8_issue_i [4] \dm7_issue_i [4] \dm6_issue_i [4] \dm5_issue_i [4] \dm4_issue_i [4] \dm3_issue_i [4] \dm2_issue_i [4] \dm1_issue_i [4] \dm0_issue_i [4] } \issue_i
    assign { \dm29_issue_i [5] \dm28_issue_i [5] \dm27_issue_i [5] \dm26_issue_i [5] \dm25_issue_i [5] \dm24_issue_i [5] \dm23_issue_i [5] \dm22_issue_i [5] \dm21_issue_i [5] \dm20_issue_i [5] \dm19_issue_i [5] \dm18_issue_i [5] \dm17_issue_i [5] \dm16_issue_i [5] \dm15_issue_i [5] \dm14_issue_i [5] \dm13_issue_i [5] \dm12_issue_i [5] \dm11_issue_i [5] \dm10_issue_i [5] \dm9_issue_i [5] \dm8_issue_i [5] \dm7_issue_i [5] \dm6_issue_i [5] \dm5_issue_i [5] \dm4_issue_i [5] \dm3_issue_i [5] \dm2_issue_i [5] \dm1_issue_i [5] \dm0_issue_i [5] } \issue_i
    assign { \dm29_issue_i [6] \dm28_issue_i [6] \dm27_issue_i [6] \dm26_issue_i [6] \dm25_issue_i [6] \dm24_issue_i [6] \dm23_issue_i [6] \dm22_issue_i [6] \dm21_issue_i [6] \dm20_issue_i [6] \dm19_issue_i [6] \dm18_issue_i [6] \dm17_issue_i [6] \dm16_issue_i [6] \dm15_issue_i [6] \dm14_issue_i [6] \dm13_issue_i [6] \dm12_issue_i [6] \dm11_issue_i [6] \dm10_issue_i [6] \dm9_issue_i [6] \dm8_issue_i [6] \dm7_issue_i [6] \dm6_issue_i [6] \dm5_issue_i [6] \dm4_issue_i [6] \dm3_issue_i [6] \dm2_issue_i [6] \dm1_issue_i [6] \dm0_issue_i [6] } \issue_i
    assign { \dm29_issue_i [7] \dm28_issue_i [7] \dm27_issue_i [7] \dm26_issue_i [7] \dm25_issue_i [7] \dm24_issue_i [7] \dm23_issue_i [7] \dm22_issue_i [7] \dm21_issue_i [7] \dm20_issue_i [7] \dm19_issue_i [7] \dm18_issue_i [7] \dm17_issue_i [7] \dm16_issue_i [7] \dm15_issue_i [7] \dm14_issue_i [7] \dm13_issue_i [7] \dm12_issue_i [7] \dm11_issue_i [7] \dm10_issue_i [7] \dm9_issue_i [7] \dm8_issue_i [7] \dm7_issue_i [7] \dm6_issue_i [7] \dm5_issue_i [7] \dm4_issue_i [7] \dm3_issue_i [7] \dm2_issue_i [7] \dm1_issue_i [7] \dm0_issue_i [7] } \issue_i
    assign { \dm29_issue_i [8] \dm28_issue_i [8] \dm27_issue_i [8] \dm26_issue_i [8] \dm25_issue_i [8] \dm24_issue_i [8] \dm23_issue_i [8] \dm22_issue_i [8] \dm21_issue_i [8] \dm20_issue_i [8] \dm19_issue_i [8] \dm18_issue_i [8] \dm17_issue_i [8] \dm16_issue_i [8] \dm15_issue_i [8] \dm14_issue_i [8] \dm13_issue_i [8] \dm12_issue_i [8] \dm11_issue_i [8] \dm10_issue_i [8] \dm9_issue_i [8] \dm8_issue_i [8] \dm7_issue_i [8] \dm6_issue_i [8] \dm5_issue_i [8] \dm4_issue_i [8] \dm3_issue_i [8] \dm2_issue_i [8] \dm1_issue_i [8] \dm0_issue_i [8] } \issue_i
    assign { \dm29_issue_i [9] \dm28_issue_i [9] \dm27_issue_i [9] \dm26_issue_i [9] \dm25_issue_i [9] \dm24_issue_i [9] \dm23_issue_i [9] \dm22_issue_i [9] \dm21_issue_i [9] \dm20_issue_i [9] \dm19_issue_i [9] \dm18_issue_i [9] \dm17_issue_i [9] \dm16_issue_i [9] \dm15_issue_i [9] \dm14_issue_i [9] \dm13_issue_i [9] \dm12_issue_i [9] \dm11_issue_i [9] \dm10_issue_i [9] \dm9_issue_i [9] \dm8_issue_i [9] \dm7_issue_i [9] \dm6_issue_i [9] \dm5_issue_i [9] \dm4_issue_i [9] \dm3_issue_i [9] \dm2_issue_i [9] \dm1_issue_i [9] \dm0_issue_i [9] } \issue_i
    assign { \dm29_issue_i [10] \dm28_issue_i [10] \dm27_issue_i [10] \dm26_issue_i [10] \dm25_issue_i [10] \dm24_issue_i [10] \dm23_issue_i [10] \dm22_issue_i [10] \dm21_issue_i [10] \dm20_issue_i [10] \dm19_issue_i [10] \dm18_issue_i [10] \dm17_issue_i [10] \dm16_issue_i [10] \dm15_issue_i [10] \dm14_issue_i [10] \dm13_issue_i [10] \dm12_issue_i [10] \dm11_issue_i [10] \dm10_issue_i [10] \dm9_issue_i [10] \dm8_issue_i [10] \dm7_issue_i [10] \dm6_issue_i [10] \dm5_issue_i [10] \dm4_issue_i [10] \dm3_issue_i [10] \dm2_issue_i [10] \dm1_issue_i [10] \dm0_issue_i [10] } \issue_i
    assign { \dm29_issue_i [11] \dm28_issue_i [11] \dm27_issue_i [11] \dm26_issue_i [11] \dm25_issue_i [11] \dm24_issue_i [11] \dm23_issue_i [11] \dm22_issue_i [11] \dm21_issue_i [11] \dm20_issue_i [11] \dm19_issue_i [11] \dm18_issue_i [11] \dm17_issue_i [11] \dm16_issue_i [11] \dm15_issue_i [11] \dm14_issue_i [11] \dm13_issue_i [11] \dm12_issue_i [11] \dm11_issue_i [11] \dm10_issue_i [11] \dm9_issue_i [11] \dm8_issue_i [11] \dm7_issue_i [11] \dm6_issue_i [11] \dm5_issue_i [11] \dm4_issue_i [11] \dm3_issue_i [11] \dm2_issue_i [11] \dm1_issue_i [11] \dm0_issue_i [11] } \issue_i
    assign { \dm29_issue_i [12] \dm28_issue_i [12] \dm27_issue_i [12] \dm26_issue_i [12] \dm25_issue_i [12] \dm24_issue_i [12] \dm23_issue_i [12] \dm22_issue_i [12] \dm21_issue_i [12] \dm20_issue_i [12] \dm19_issue_i [12] \dm18_issue_i [12] \dm17_issue_i [12] \dm16_issue_i [12] \dm15_issue_i [12] \dm14_issue_i [12] \dm13_issue_i [12] \dm12_issue_i [12] \dm11_issue_i [12] \dm10_issue_i [12] \dm9_issue_i [12] \dm8_issue_i [12] \dm7_issue_i [12] \dm6_issue_i [12] \dm5_issue_i [12] \dm4_issue_i [12] \dm3_issue_i [12] \dm2_issue_i [12] \dm1_issue_i [12] \dm0_issue_i [12] } \issue_i
    assign { \dm29_issue_i [13] \dm28_issue_i [13] \dm27_issue_i [13] \dm26_issue_i [13] \dm25_issue_i [13] \dm24_issue_i [13] \dm23_issue_i [13] \dm22_issue_i [13] \dm21_issue_i [13] \dm20_issue_i [13] \dm19_issue_i [13] \dm18_issue_i [13] \dm17_issue_i [13] \dm16_issue_i [13] \dm15_issue_i [13] \dm14_issue_i [13] \dm13_issue_i [13] \dm12_issue_i [13] \dm11_issue_i [13] \dm10_issue_i [13] \dm9_issue_i [13] \dm8_issue_i [13] \dm7_issue_i [13] \dm6_issue_i [13] \dm5_issue_i [13] \dm4_issue_i [13] \dm3_issue_i [13] \dm2_issue_i [13] \dm1_issue_i [13] \dm0_issue_i [13] } \issue_i
    assign { \dm29_issue_i [14] \dm28_issue_i [14] \dm27_issue_i [14] \dm26_issue_i [14] \dm25_issue_i [14] \dm24_issue_i [14] \dm23_issue_i [14] \dm22_issue_i [14] \dm21_issue_i [14] \dm20_issue_i [14] \dm19_issue_i [14] \dm18_issue_i [14] \dm17_issue_i [14] \dm16_issue_i [14] \dm15_issue_i [14] \dm14_issue_i [14] \dm13_issue_i [14] \dm12_issue_i [14] \dm11_issue_i [14] \dm10_issue_i [14] \dm9_issue_i [14] \dm8_issue_i [14] \dm7_issue_i [14] \dm6_issue_i [14] \dm5_issue_i [14] \dm4_issue_i [14] \dm3_issue_i [14] \dm2_issue_i [14] \dm1_issue_i [14] \dm0_issue_i [14] } \issue_i
    assign { \dm29_issue_i [15] \dm28_issue_i [15] \dm27_issue_i [15] \dm26_issue_i [15] \dm25_issue_i [15] \dm24_issue_i [15] \dm23_issue_i [15] \dm22_issue_i [15] \dm21_issue_i [15] \dm20_issue_i [15] \dm19_issue_i [15] \dm18_issue_i [15] \dm17_issue_i [15] \dm16_issue_i [15] \dm15_issue_i [15] \dm14_issue_i [15] \dm13_issue_i [15] \dm12_issue_i [15] \dm11_issue_i [15] \dm10_issue_i [15] \dm9_issue_i [15] \dm8_issue_i [15] \dm7_issue_i [15] \dm6_issue_i [15] \dm5_issue_i [15] \dm4_issue_i [15] \dm3_issue_i [15] \dm2_issue_i [15] \dm1_issue_i [15] \dm0_issue_i [15] } \issue_i
    assign { \dm29_issue_i [16] \dm28_issue_i [16] \dm27_issue_i [16] \dm26_issue_i [16] \dm25_issue_i [16] \dm24_issue_i [16] \dm23_issue_i [16] \dm22_issue_i [16] \dm21_issue_i [16] \dm20_issue_i [16] \dm19_issue_i [16] \dm18_issue_i [16] \dm17_issue_i [16] \dm16_issue_i [16] \dm15_issue_i [16] \dm14_issue_i [16] \dm13_issue_i [16] \dm12_issue_i [16] \dm11_issue_i [16] \dm10_issue_i [16] \dm9_issue_i [16] \dm8_issue_i [16] \dm7_issue_i [16] \dm6_issue_i [16] \dm5_issue_i [16] \dm4_issue_i [16] \dm3_issue_i [16] \dm2_issue_i [16] \dm1_issue_i [16] \dm0_issue_i [16] } \issue_i
    assign { \dm29_issue_i [17] \dm28_issue_i [17] \dm27_issue_i [17] \dm26_issue_i [17] \dm25_issue_i [17] \dm24_issue_i [17] \dm23_issue_i [17] \dm22_issue_i [17] \dm21_issue_i [17] \dm20_issue_i [17] \dm19_issue_i [17] \dm18_issue_i [17] \dm17_issue_i [17] \dm16_issue_i [17] \dm15_issue_i [17] \dm14_issue_i [17] \dm13_issue_i [17] \dm12_issue_i [17] \dm11_issue_i [17] \dm10_issue_i [17] \dm9_issue_i [17] \dm8_issue_i [17] \dm7_issue_i [17] \dm6_issue_i [17] \dm5_issue_i [17] \dm4_issue_i [17] \dm3_issue_i [17] \dm2_issue_i [17] \dm1_issue_i [17] \dm0_issue_i [17] } \issue_i
    assign { \dm29_issue_i [18] \dm28_issue_i [18] \dm27_issue_i [18] \dm26_issue_i [18] \dm25_issue_i [18] \dm24_issue_i [18] \dm23_issue_i [18] \dm22_issue_i [18] \dm21_issue_i [18] \dm20_issue_i [18] \dm19_issue_i [18] \dm18_issue_i [18] \dm17_issue_i [18] \dm16_issue_i [18] \dm15_issue_i [18] \dm14_issue_i [18] \dm13_issue_i [18] \dm12_issue_i [18] \dm11_issue_i [18] \dm10_issue_i [18] \dm9_issue_i [18] \dm8_issue_i [18] \dm7_issue_i [18] \dm6_issue_i [18] \dm5_issue_i [18] \dm4_issue_i [18] \dm3_issue_i [18] \dm2_issue_i [18] \dm1_issue_i [18] \dm0_issue_i [18] } \issue_i
    assign { \dm29_issue_i [19] \dm28_issue_i [19] \dm27_issue_i [19] \dm26_issue_i [19] \dm25_issue_i [19] \dm24_issue_i [19] \dm23_issue_i [19] \dm22_issue_i [19] \dm21_issue_i [19] \dm20_issue_i [19] \dm19_issue_i [19] \dm18_issue_i [19] \dm17_issue_i [19] \dm16_issue_i [19] \dm15_issue_i [19] \dm14_issue_i [19] \dm13_issue_i [19] \dm12_issue_i [19] \dm11_issue_i [19] \dm10_issue_i [19] \dm9_issue_i [19] \dm8_issue_i [19] \dm7_issue_i [19] \dm6_issue_i [19] \dm5_issue_i [19] \dm4_issue_i [19] \dm3_issue_i [19] \dm2_issue_i [19] \dm1_issue_i [19] \dm0_issue_i [19] } \issue_i
    assign { \dm29_issue_i [20] \dm28_issue_i [20] \dm27_issue_i [20] \dm26_issue_i [20] \dm25_issue_i [20] \dm24_issue_i [20] \dm23_issue_i [20] \dm22_issue_i [20] \dm21_issue_i [20] \dm20_issue_i [20] \dm19_issue_i [20] \dm18_issue_i [20] \dm17_issue_i [20] \dm16_issue_i [20] \dm15_issue_i [20] \dm14_issue_i [20] \dm13_issue_i [20] \dm12_issue_i [20] \dm11_issue_i [20] \dm10_issue_i [20] \dm9_issue_i [20] \dm8_issue_i [20] \dm7_issue_i [20] \dm6_issue_i [20] \dm5_issue_i [20] \dm4_issue_i [20] \dm3_issue_i [20] \dm2_issue_i [20] \dm1_issue_i [20] \dm0_issue_i [20] } \issue_i
    assign { \dm29_issue_i [21] \dm28_issue_i [21] \dm27_issue_i [21] \dm26_issue_i [21] \dm25_issue_i [21] \dm24_issue_i [21] \dm23_issue_i [21] \dm22_issue_i [21] \dm21_issue_i [21] \dm20_issue_i [21] \dm19_issue_i [21] \dm18_issue_i [21] \dm17_issue_i [21] \dm16_issue_i [21] \dm15_issue_i [21] \dm14_issue_i [21] \dm13_issue_i [21] \dm12_issue_i [21] \dm11_issue_i [21] \dm10_issue_i [21] \dm9_issue_i [21] \dm8_issue_i [21] \dm7_issue_i [21] \dm6_issue_i [21] \dm5_issue_i [21] \dm4_issue_i [21] \dm3_issue_i [21] \dm2_issue_i [21] \dm1_issue_i [21] \dm0_issue_i [21] } \issue_i
    assign { \dm29_issue_i [22] \dm28_issue_i [22] \dm27_issue_i [22] \dm26_issue_i [22] \dm25_issue_i [22] \dm24_issue_i [22] \dm23_issue_i [22] \dm22_issue_i [22] \dm21_issue_i [22] \dm20_issue_i [22] \dm19_issue_i [22] \dm18_issue_i [22] \dm17_issue_i [22] \dm16_issue_i [22] \dm15_issue_i [22] \dm14_issue_i [22] \dm13_issue_i [22] \dm12_issue_i [22] \dm11_issue_i [22] \dm10_issue_i [22] \dm9_issue_i [22] \dm8_issue_i [22] \dm7_issue_i [22] \dm6_issue_i [22] \dm5_issue_i [22] \dm4_issue_i [22] \dm3_issue_i [22] \dm2_issue_i [22] \dm1_issue_i [22] \dm0_issue_i [22] } \issue_i
    assign { \dm29_issue_i [23] \dm28_issue_i [23] \dm27_issue_i [23] \dm26_issue_i [23] \dm25_issue_i [23] \dm24_issue_i [23] \dm23_issue_i [23] \dm22_issue_i [23] \dm21_issue_i [23] \dm20_issue_i [23] \dm19_issue_i [23] \dm18_issue_i [23] \dm17_issue_i [23] \dm16_issue_i [23] \dm15_issue_i [23] \dm14_issue_i [23] \dm13_issue_i [23] \dm12_issue_i [23] \dm11_issue_i [23] \dm10_issue_i [23] \dm9_issue_i [23] \dm8_issue_i [23] \dm7_issue_i [23] \dm6_issue_i [23] \dm5_issue_i [23] \dm4_issue_i [23] \dm3_issue_i [23] \dm2_issue_i [23] \dm1_issue_i [23] \dm0_issue_i [23] } \issue_i
    assign { \dm29_issue_i [24] \dm28_issue_i [24] \dm27_issue_i [24] \dm26_issue_i [24] \dm25_issue_i [24] \dm24_issue_i [24] \dm23_issue_i [24] \dm22_issue_i [24] \dm21_issue_i [24] \dm20_issue_i [24] \dm19_issue_i [24] \dm18_issue_i [24] \dm17_issue_i [24] \dm16_issue_i [24] \dm15_issue_i [24] \dm14_issue_i [24] \dm13_issue_i [24] \dm12_issue_i [24] \dm11_issue_i [24] \dm10_issue_i [24] \dm9_issue_i [24] \dm8_issue_i [24] \dm7_issue_i [24] \dm6_issue_i [24] \dm5_issue_i [24] \dm4_issue_i [24] \dm3_issue_i [24] \dm2_issue_i [24] \dm1_issue_i [24] \dm0_issue_i [24] } \issue_i
    assign { \dm29_issue_i [25] \dm28_issue_i [25] \dm27_issue_i [25] \dm26_issue_i [25] \dm25_issue_i [25] \dm24_issue_i [25] \dm23_issue_i [25] \dm22_issue_i [25] \dm21_issue_i [25] \dm20_issue_i [25] \dm19_issue_i [25] \dm18_issue_i [25] \dm17_issue_i [25] \dm16_issue_i [25] \dm15_issue_i [25] \dm14_issue_i [25] \dm13_issue_i [25] \dm12_issue_i [25] \dm11_issue_i [25] \dm10_issue_i [25] \dm9_issue_i [25] \dm8_issue_i [25] \dm7_issue_i [25] \dm6_issue_i [25] \dm5_issue_i [25] \dm4_issue_i [25] \dm3_issue_i [25] \dm2_issue_i [25] \dm1_issue_i [25] \dm0_issue_i [25] } \issue_i
    assign { \dm29_issue_i [26] \dm28_issue_i [26] \dm27_issue_i [26] \dm26_issue_i [26] \dm25_issue_i [26] \dm24_issue_i [26] \dm23_issue_i [26] \dm22_issue_i [26] \dm21_issue_i [26] \dm20_issue_i [26] \dm19_issue_i [26] \dm18_issue_i [26] \dm17_issue_i [26] \dm16_issue_i [26] \dm15_issue_i [26] \dm14_issue_i [26] \dm13_issue_i [26] \dm12_issue_i [26] \dm11_issue_i [26] \dm10_issue_i [26] \dm9_issue_i [26] \dm8_issue_i [26] \dm7_issue_i [26] \dm6_issue_i [26] \dm5_issue_i [26] \dm4_issue_i [26] \dm3_issue_i [26] \dm2_issue_i [26] \dm1_issue_i [26] \dm0_issue_i [26] } \issue_i
    assign { \dm29_issue_i [27] \dm28_issue_i [27] \dm27_issue_i [27] \dm26_issue_i [27] \dm25_issue_i [27] \dm24_issue_i [27] \dm23_issue_i [27] \dm22_issue_i [27] \dm21_issue_i [27] \dm20_issue_i [27] \dm19_issue_i [27] \dm18_issue_i [27] \dm17_issue_i [27] \dm16_issue_i [27] \dm15_issue_i [27] \dm14_issue_i [27] \dm13_issue_i [27] \dm12_issue_i [27] \dm11_issue_i [27] \dm10_issue_i [27] \dm9_issue_i [27] \dm8_issue_i [27] \dm7_issue_i [27] \dm6_issue_i [27] \dm5_issue_i [27] \dm4_issue_i [27] \dm3_issue_i [27] \dm2_issue_i [27] \dm1_issue_i [27] \dm0_issue_i [27] } \issue_i
    assign { \dm29_issue_i [28] \dm28_issue_i [28] \dm27_issue_i [28] \dm26_issue_i [28] \dm25_issue_i [28] \dm24_issue_i [28] \dm23_issue_i [28] \dm22_issue_i [28] \dm21_issue_i [28] \dm20_issue_i [28] \dm19_issue_i [28] \dm18_issue_i [28] \dm17_issue_i [28] \dm16_issue_i [28] \dm15_issue_i [28] \dm14_issue_i [28] \dm13_issue_i [28] \dm12_issue_i [28] \dm11_issue_i [28] \dm10_issue_i [28] \dm9_issue_i [28] \dm8_issue_i [28] \dm7_issue_i [28] \dm6_issue_i [28] \dm5_issue_i [28] \dm4_issue_i [28] \dm3_issue_i [28] \dm2_issue_i [28] \dm1_issue_i [28] \dm0_issue_i [28] } \issue_i
    assign { \dm29_issue_i [29] \dm28_issue_i [29] \dm27_issue_i [29] \dm26_issue_i [29] \dm25_issue_i [29] \dm24_issue_i [29] \dm23_issue_i [29] \dm22_issue_i [29] \dm21_issue_i [29] \dm20_issue_i [29] \dm19_issue_i [29] \dm18_issue_i [29] \dm17_issue_i [29] \dm16_issue_i [29] \dm15_issue_i [29] \dm14_issue_i [29] \dm13_issue_i [29] \dm12_issue_i [29] \dm11_issue_i [29] \dm10_issue_i [29] \dm9_issue_i [29] \dm8_issue_i [29] \dm7_issue_i [29] \dm6_issue_i [29] \dm5_issue_i [29] \dm4_issue_i [29] \dm3_issue_i [29] \dm2_issue_i [29] \dm1_issue_i [29] \dm0_issue_i [29] } \issue_i
    sync init
  end
  process $group_92
    assign \dm0_go_die_i 30'000000000000000000000000000000
    assign \dm0_go_die_i \go_die_i
    sync init
  end
  process $group_93
    assign \dm0_gord1_i 30'000000000000000000000000000000
    assign \dm0_gord1_i \gord1_i
    sync init
  end
  process $group_94
    assign \dm0_gord2_i 30'000000000000000000000000000000
    assign \dm0_gord2_i \gord2_i
    sync init
  end
  process $group_95
    assign \dm0_gord3_i 30'000000000000000000000000000000
    assign \dm0_gord3_i \gord3_i
    sync init
  end
  process $group_96
    assign \dm0_gowr1_i 30'000000000000000000000000000000
    assign \dm0_gowr1_i \gowr1_i
    sync init
  end
  process $group_97
    assign \dm0_gowr2_i 30'000000000000000000000000000000
    assign \dm0_gowr2_i \gowr2_i
    sync init
  end
  process $group_98
    assign \dm1_go_die_i 30'000000000000000000000000000000
    assign \dm1_go_die_i \go_die_i
    sync init
  end
  process $group_99
    assign \dm1_gord1_i 30'000000000000000000000000000000
    assign \dm1_gord1_i \gord1_i
    sync init
  end
  process $group_100
    assign \dm1_gord2_i 30'000000000000000000000000000000
    assign \dm1_gord2_i \gord2_i
    sync init
  end
  process $group_101
    assign \dm1_gord3_i 30'000000000000000000000000000000
    assign \dm1_gord3_i \gord3_i
    sync init
  end
  process $group_102
    assign \dm1_gowr1_i 30'000000000000000000000000000000
    assign \dm1_gowr1_i \gowr1_i
    sync init
  end
  process $group_103
    assign \dm1_gowr2_i 30'000000000000000000000000000000
    assign \dm1_gowr2_i \gowr2_i
    sync init
  end
  process $group_104
    assign \dm2_go_die_i 30'000000000000000000000000000000
    assign \dm2_go_die_i \go_die_i
    sync init
  end
  process $group_105
    assign \dm2_gord1_i 30'000000000000000000000000000000
    assign \dm2_gord1_i \gord1_i
    sync init
  end
  process $group_106
    assign \dm2_gord2_i 30'000000000000000000000000000000
    assign \dm2_gord2_i \gord2_i
    sync init
  end
  process $group_107
    assign \dm2_gord3_i 30'000000000000000000000000000000
    assign \dm2_gord3_i \gord3_i
    sync init
  end
  process $group_108
    assign \dm2_gowr1_i 30'000000000000000000000000000000
    assign \dm2_gowr1_i \gowr1_i
    sync init
  end
  process $group_109
    assign \dm2_gowr2_i 30'000000000000000000000000000000
    assign \dm2_gowr2_i \gowr2_i
    sync init
  end
  process $group_110
    assign \dm3_go_die_i 30'000000000000000000000000000000
    assign \dm3_go_die_i \go_die_i
    sync init
  end
  process $group_111
    assign \dm3_gord1_i 30'000000000000000000000000000000
    assign \dm3_gord1_i \gord1_i
    sync init
  end
  process $group_112
    assign \dm3_gord2_i 30'000000000000000000000000000000
    assign \dm3_gord2_i \gord2_i
    sync init
  end
  process $group_113
    assign \dm3_gord3_i 30'000000000000000000000000000000
    assign \dm3_gord3_i \gord3_i
    sync init
  end
  process $group_114
    assign \dm3_gowr1_i 30'000000000000000000000000000000
    assign \dm3_gowr1_i \gowr1_i
    sync init
  end
  process $group_115
    assign \dm3_gowr2_i 30'000000000000000000000000000000
    assign \dm3_gowr2_i \gowr2_i
    sync init
  end
  process $group_116
    assign \dm4_go_die_i 30'000000000000000000000000000000
    assign \dm4_go_die_i \go_die_i
    sync init
  end
  process $group_117
    assign \dm4_gord1_i 30'000000000000000000000000000000
    assign \dm4_gord1_i \gord1_i
    sync init
  end
  process $group_118
    assign \dm4_gord2_i 30'000000000000000000000000000000
    assign \dm4_gord2_i \gord2_i
    sync init
  end
  process $group_119
    assign \dm4_gord3_i 30'000000000000000000000000000000
    assign \dm4_gord3_i \gord3_i
    sync init
  end
  process $group_120
    assign \dm4_gowr1_i 30'000000000000000000000000000000
    assign \dm4_gowr1_i \gowr1_i
    sync init
  end
  process $group_121
    assign \dm4_gowr2_i 30'000000000000000000000000000000
    assign \dm4_gowr2_i \gowr2_i
    sync init
  end
  process $group_122
    assign \dm5_go_die_i 30'000000000000000000000000000000
    assign \dm5_go_die_i \go_die_i
    sync init
  end
  process $group_123
    assign \dm5_gord1_i 30'000000000000000000000000000000
    assign \dm5_gord1_i \gord1_i
    sync init
  end
  process $group_124
    assign \dm5_gord2_i 30'000000000000000000000000000000
    assign \dm5_gord2_i \gord2_i
    sync init
  end
  process $group_125
    assign \dm5_gord3_i 30'000000000000000000000000000000
    assign \dm5_gord3_i \gord3_i
    sync init
  end
  process $group_126
    assign \dm5_gowr1_i 30'000000000000000000000000000000
    assign \dm5_gowr1_i \gowr1_i
    sync init
  end
  process $group_127
    assign \dm5_gowr2_i 30'000000000000000000000000000000
    assign \dm5_gowr2_i \gowr2_i
    sync init
  end
  process $group_128
    assign \dm6_go_die_i 30'000000000000000000000000000000
    assign \dm6_go_die_i \go_die_i
    sync init
  end
  process $group_129
    assign \dm6_gord1_i 30'000000000000000000000000000000
    assign \dm6_gord1_i \gord1_i
    sync init
  end
  process $group_130
    assign \dm6_gord2_i 30'000000000000000000000000000000
    assign \dm6_gord2_i \gord2_i
    sync init
  end
  process $group_131
    assign \dm6_gord3_i 30'000000000000000000000000000000
    assign \dm6_gord3_i \gord3_i
    sync init
  end
  process $group_132
    assign \dm6_gowr1_i 30'000000000000000000000000000000
    assign \dm6_gowr1_i \gowr1_i
    sync init
  end
  process $group_133
    assign \dm6_gowr2_i 30'000000000000000000000000000000
    assign \dm6_gowr2_i \gowr2_i
    sync init
  end
  process $group_134
    assign \dm7_go_die_i 30'000000000000000000000000000000
    assign \dm7_go_die_i \go_die_i
    sync init
  end
  process $group_135
    assign \dm7_gord1_i 30'000000000000000000000000000000
    assign \dm7_gord1_i \gord1_i
    sync init
  end
  process $group_136
    assign \dm7_gord2_i 30'000000000000000000000000000000
    assign \dm7_gord2_i \gord2_i
    sync init
  end
  process $group_137
    assign \dm7_gord3_i 30'000000000000000000000000000000
    assign \dm7_gord3_i \gord3_i
    sync init
  end
  process $group_138
    assign \dm7_gowr1_i 30'000000000000000000000000000000
    assign \dm7_gowr1_i \gowr1_i
    sync init
  end
  process $group_139
    assign \dm7_gowr2_i 30'000000000000000000000000000000
    assign \dm7_gowr2_i \gowr2_i
    sync init
  end
  process $group_140
    assign \dm8_go_die_i 30'000000000000000000000000000000
    assign \dm8_go_die_i \go_die_i
    sync init
  end
  process $group_141
    assign \dm8_gord1_i 30'000000000000000000000000000000
    assign \dm8_gord1_i \gord1_i
    sync init
  end
  process $group_142
    assign \dm8_gord2_i 30'000000000000000000000000000000
    assign \dm8_gord2_i \gord2_i
    sync init
  end
  process $group_143
    assign \dm8_gord3_i 30'000000000000000000000000000000
    assign \dm8_gord3_i \gord3_i
    sync init
  end
  process $group_144
    assign \dm8_gowr1_i 30'000000000000000000000000000000
    assign \dm8_gowr1_i \gowr1_i
    sync init
  end
  process $group_145
    assign \dm8_gowr2_i 30'000000000000000000000000000000
    assign \dm8_gowr2_i \gowr2_i
    sync init
  end
  process $group_146
    assign \dm9_go_die_i 30'000000000000000000000000000000
    assign \dm9_go_die_i \go_die_i
    sync init
  end
  process $group_147
    assign \dm9_gord1_i 30'000000000000000000000000000000
    assign \dm9_gord1_i \gord1_i
    sync init
  end
  process $group_148
    assign \dm9_gord2_i 30'000000000000000000000000000000
    assign \dm9_gord2_i \gord2_i
    sync init
  end
  process $group_149
    assign \dm9_gord3_i 30'000000000000000000000000000000
    assign \dm9_gord3_i \gord3_i
    sync init
  end
  process $group_150
    assign \dm9_gowr1_i 30'000000000000000000000000000000
    assign \dm9_gowr1_i \gowr1_i
    sync init
  end
  process $group_151
    assign \dm9_gowr2_i 30'000000000000000000000000000000
    assign \dm9_gowr2_i \gowr2_i
    sync init
  end
  process $group_152
    assign \dm10_go_die_i 30'000000000000000000000000000000
    assign \dm10_go_die_i \go_die_i
    sync init
  end
  process $group_153
    assign \dm10_gord1_i 30'000000000000000000000000000000
    assign \dm10_gord1_i \gord1_i
    sync init
  end
  process $group_154
    assign \dm10_gord2_i 30'000000000000000000000000000000
    assign \dm10_gord2_i \gord2_i
    sync init
  end
  process $group_155
    assign \dm10_gord3_i 30'000000000000000000000000000000
    assign \dm10_gord3_i \gord3_i
    sync init
  end
  process $group_156
    assign \dm10_gowr1_i 30'000000000000000000000000000000
    assign \dm10_gowr1_i \gowr1_i
    sync init
  end
  process $group_157
    assign \dm10_gowr2_i 30'000000000000000000000000000000
    assign \dm10_gowr2_i \gowr2_i
    sync init
  end
  process $group_158
    assign \dm11_go_die_i 30'000000000000000000000000000000
    assign \dm11_go_die_i \go_die_i
    sync init
  end
  process $group_159
    assign \dm11_gord1_i 30'000000000000000000000000000000
    assign \dm11_gord1_i \gord1_i
    sync init
  end
  process $group_160
    assign \dm11_gord2_i 30'000000000000000000000000000000
    assign \dm11_gord2_i \gord2_i
    sync init
  end
  process $group_161
    assign \dm11_gord3_i 30'000000000000000000000000000000
    assign \dm11_gord3_i \gord3_i
    sync init
  end
  process $group_162
    assign \dm11_gowr1_i 30'000000000000000000000000000000
    assign \dm11_gowr1_i \gowr1_i
    sync init
  end
  process $group_163
    assign \dm11_gowr2_i 30'000000000000000000000000000000
    assign \dm11_gowr2_i \gowr2_i
    sync init
  end
  process $group_164
    assign \dm12_go_die_i 30'000000000000000000000000000000
    assign \dm12_go_die_i \go_die_i
    sync init
  end
  process $group_165
    assign \dm12_gord1_i 30'000000000000000000000000000000
    assign \dm12_gord1_i \gord1_i
    sync init
  end
  process $group_166
    assign \dm12_gord2_i 30'000000000000000000000000000000
    assign \dm12_gord2_i \gord2_i
    sync init
  end
  process $group_167
    assign \dm12_gord3_i 30'000000000000000000000000000000
    assign \dm12_gord3_i \gord3_i
    sync init
  end
  process $group_168
    assign \dm12_gowr1_i 30'000000000000000000000000000000
    assign \dm12_gowr1_i \gowr1_i
    sync init
  end
  process $group_169
    assign \dm12_gowr2_i 30'000000000000000000000000000000
    assign \dm12_gowr2_i \gowr2_i
    sync init
  end
  process $group_170
    assign \dm13_go_die_i 30'000000000000000000000000000000
    assign \dm13_go_die_i \go_die_i
    sync init
  end
  process $group_171
    assign \dm13_gord1_i 30'000000000000000000000000000000
    assign \dm13_gord1_i \gord1_i
    sync init
  end
  process $group_172
    assign \dm13_gord2_i 30'000000000000000000000000000000
    assign \dm13_gord2_i \gord2_i
    sync init
  end
  process $group_173
    assign \dm13_gord3_i 30'000000000000000000000000000000
    assign \dm13_gord3_i \gord3_i
    sync init
  end
  process $group_174
    assign \dm13_gowr1_i 30'000000000000000000000000000000
    assign \dm13_gowr1_i \gowr1_i
    sync init
  end
  process $group_175
    assign \dm13_gowr2_i 30'000000000000000000000000000000
    assign \dm13_gowr2_i \gowr2_i
    sync init
  end
  process $group_176
    assign \dm14_go_die_i 30'000000000000000000000000000000
    assign \dm14_go_die_i \go_die_i
    sync init
  end
  process $group_177
    assign \dm14_gord1_i 30'000000000000000000000000000000
    assign \dm14_gord1_i \gord1_i
    sync init
  end
  process $group_178
    assign \dm14_gord2_i 30'000000000000000000000000000000
    assign \dm14_gord2_i \gord2_i
    sync init
  end
  process $group_179
    assign \dm14_gord3_i 30'000000000000000000000000000000
    assign \dm14_gord3_i \gord3_i
    sync init
  end
  process $group_180
    assign \dm14_gowr1_i 30'000000000000000000000000000000
    assign \dm14_gowr1_i \gowr1_i
    sync init
  end
  process $group_181
    assign \dm14_gowr2_i 30'000000000000000000000000000000
    assign \dm14_gowr2_i \gowr2_i
    sync init
  end
  process $group_182
    assign \dm15_go_die_i 30'000000000000000000000000000000
    assign \dm15_go_die_i \go_die_i
    sync init
  end
  process $group_183
    assign \dm15_gord1_i 30'000000000000000000000000000000
    assign \dm15_gord1_i \gord1_i
    sync init
  end
  process $group_184
    assign \dm15_gord2_i 30'000000000000000000000000000000
    assign \dm15_gord2_i \gord2_i
    sync init
  end
  process $group_185
    assign \dm15_gord3_i 30'000000000000000000000000000000
    assign \dm15_gord3_i \gord3_i
    sync init
  end
  process $group_186
    assign \dm15_gowr1_i 30'000000000000000000000000000000
    assign \dm15_gowr1_i \gowr1_i
    sync init
  end
  process $group_187
    assign \dm15_gowr2_i 30'000000000000000000000000000000
    assign \dm15_gowr2_i \gowr2_i
    sync init
  end
  process $group_188
    assign \dm16_go_die_i 30'000000000000000000000000000000
    assign \dm16_go_die_i \go_die_i
    sync init
  end
  process $group_189
    assign \dm16_gord1_i 30'000000000000000000000000000000
    assign \dm16_gord1_i \gord1_i
    sync init
  end
  process $group_190
    assign \dm16_gord2_i 30'000000000000000000000000000000
    assign \dm16_gord2_i \gord2_i
    sync init
  end
  process $group_191
    assign \dm16_gord3_i 30'000000000000000000000000000000
    assign \dm16_gord3_i \gord3_i
    sync init
  end
  process $group_192
    assign \dm16_gowr1_i 30'000000000000000000000000000000
    assign \dm16_gowr1_i \gowr1_i
    sync init
  end
  process $group_193
    assign \dm16_gowr2_i 30'000000000000000000000000000000
    assign \dm16_gowr2_i \gowr2_i
    sync init
  end
  process $group_194
    assign \dm17_go_die_i 30'000000000000000000000000000000
    assign \dm17_go_die_i \go_die_i
    sync init
  end
  process $group_195
    assign \dm17_gord1_i 30'000000000000000000000000000000
    assign \dm17_gord1_i \gord1_i
    sync init
  end
  process $group_196
    assign \dm17_gord2_i 30'000000000000000000000000000000
    assign \dm17_gord2_i \gord2_i
    sync init
  end
  process $group_197
    assign \dm17_gord3_i 30'000000000000000000000000000000
    assign \dm17_gord3_i \gord3_i
    sync init
  end
  process $group_198
    assign \dm17_gowr1_i 30'000000000000000000000000000000
    assign \dm17_gowr1_i \gowr1_i
    sync init
  end
  process $group_199
    assign \dm17_gowr2_i 30'000000000000000000000000000000
    assign \dm17_gowr2_i \gowr2_i
    sync init
  end
  process $group_200
    assign \dm18_go_die_i 30'000000000000000000000000000000
    assign \dm18_go_die_i \go_die_i
    sync init
  end
  process $group_201
    assign \dm18_gord1_i 30'000000000000000000000000000000
    assign \dm18_gord1_i \gord1_i
    sync init
  end
  process $group_202
    assign \dm18_gord2_i 30'000000000000000000000000000000
    assign \dm18_gord2_i \gord2_i
    sync init
  end
  process $group_203
    assign \dm18_gord3_i 30'000000000000000000000000000000
    assign \dm18_gord3_i \gord3_i
    sync init
  end
  process $group_204
    assign \dm18_gowr1_i 30'000000000000000000000000000000
    assign \dm18_gowr1_i \gowr1_i
    sync init
  end
  process $group_205
    assign \dm18_gowr2_i 30'000000000000000000000000000000
    assign \dm18_gowr2_i \gowr2_i
    sync init
  end
  process $group_206
    assign \dm19_go_die_i 30'000000000000000000000000000000
    assign \dm19_go_die_i \go_die_i
    sync init
  end
  process $group_207
    assign \dm19_gord1_i 30'000000000000000000000000000000
    assign \dm19_gord1_i \gord1_i
    sync init
  end
  process $group_208
    assign \dm19_gord2_i 30'000000000000000000000000000000
    assign \dm19_gord2_i \gord2_i
    sync init
  end
  process $group_209
    assign \dm19_gord3_i 30'000000000000000000000000000000
    assign \dm19_gord3_i \gord3_i
    sync init
  end
  process $group_210
    assign \dm19_gowr1_i 30'000000000000000000000000000000
    assign \dm19_gowr1_i \gowr1_i
    sync init
  end
  process $group_211
    assign \dm19_gowr2_i 30'000000000000000000000000000000
    assign \dm19_gowr2_i \gowr2_i
    sync init
  end
  process $group_212
    assign \dm20_go_die_i 30'000000000000000000000000000000
    assign \dm20_go_die_i \go_die_i
    sync init
  end
  process $group_213
    assign \dm20_gord1_i 30'000000000000000000000000000000
    assign \dm20_gord1_i \gord1_i
    sync init
  end
  process $group_214
    assign \dm20_gord2_i 30'000000000000000000000000000000
    assign \dm20_gord2_i \gord2_i
    sync init
  end
  process $group_215
    assign \dm20_gord3_i 30'000000000000000000000000000000
    assign \dm20_gord3_i \gord3_i
    sync init
  end
  process $group_216
    assign \dm20_gowr1_i 30'000000000000000000000000000000
    assign \dm20_gowr1_i \gowr1_i
    sync init
  end
  process $group_217
    assign \dm20_gowr2_i 30'000000000000000000000000000000
    assign \dm20_gowr2_i \gowr2_i
    sync init
  end
  process $group_218
    assign \dm21_go_die_i 30'000000000000000000000000000000
    assign \dm21_go_die_i \go_die_i
    sync init
  end
  process $group_219
    assign \dm21_gord1_i 30'000000000000000000000000000000
    assign \dm21_gord1_i \gord1_i
    sync init
  end
  process $group_220
    assign \dm21_gord2_i 30'000000000000000000000000000000
    assign \dm21_gord2_i \gord2_i
    sync init
  end
  process $group_221
    assign \dm21_gord3_i 30'000000000000000000000000000000
    assign \dm21_gord3_i \gord3_i
    sync init
  end
  process $group_222
    assign \dm21_gowr1_i 30'000000000000000000000000000000
    assign \dm21_gowr1_i \gowr1_i
    sync init
  end
  process $group_223
    assign \dm21_gowr2_i 30'000000000000000000000000000000
    assign \dm21_gowr2_i \gowr2_i
    sync init
  end
  process $group_224
    assign \dm22_go_die_i 30'000000000000000000000000000000
    assign \dm22_go_die_i \go_die_i
    sync init
  end
  process $group_225
    assign \dm22_gord1_i 30'000000000000000000000000000000
    assign \dm22_gord1_i \gord1_i
    sync init
  end
  process $group_226
    assign \dm22_gord2_i 30'000000000000000000000000000000
    assign \dm22_gord2_i \gord2_i
    sync init
  end
  process $group_227
    assign \dm22_gord3_i 30'000000000000000000000000000000
    assign \dm22_gord3_i \gord3_i
    sync init
  end
  process $group_228
    assign \dm22_gowr1_i 30'000000000000000000000000000000
    assign \dm22_gowr1_i \gowr1_i
    sync init
  end
  process $group_229
    assign \dm22_gowr2_i 30'000000000000000000000000000000
    assign \dm22_gowr2_i \gowr2_i
    sync init
  end
  process $group_230
    assign \dm23_go_die_i 30'000000000000000000000000000000
    assign \dm23_go_die_i \go_die_i
    sync init
  end
  process $group_231
    assign \dm23_gord1_i 30'000000000000000000000000000000
    assign \dm23_gord1_i \gord1_i
    sync init
  end
  process $group_232
    assign \dm23_gord2_i 30'000000000000000000000000000000
    assign \dm23_gord2_i \gord2_i
    sync init
  end
  process $group_233
    assign \dm23_gord3_i 30'000000000000000000000000000000
    assign \dm23_gord3_i \gord3_i
    sync init
  end
  process $group_234
    assign \dm23_gowr1_i 30'000000000000000000000000000000
    assign \dm23_gowr1_i \gowr1_i
    sync init
  end
  process $group_235
    assign \dm23_gowr2_i 30'000000000000000000000000000000
    assign \dm23_gowr2_i \gowr2_i
    sync init
  end
  process $group_236
    assign \dm24_go_die_i 30'000000000000000000000000000000
    assign \dm24_go_die_i \go_die_i
    sync init
  end
  process $group_237
    assign \dm24_gord1_i 30'000000000000000000000000000000
    assign \dm24_gord1_i \gord1_i
    sync init
  end
  process $group_238
    assign \dm24_gord2_i 30'000000000000000000000000000000
    assign \dm24_gord2_i \gord2_i
    sync init
  end
  process $group_239
    assign \dm24_gord3_i 30'000000000000000000000000000000
    assign \dm24_gord3_i \gord3_i
    sync init
  end
  process $group_240
    assign \dm24_gowr1_i 30'000000000000000000000000000000
    assign \dm24_gowr1_i \gowr1_i
    sync init
  end
  process $group_241
    assign \dm24_gowr2_i 30'000000000000000000000000000000
    assign \dm24_gowr2_i \gowr2_i
    sync init
  end
  process $group_242
    assign \dm25_go_die_i 30'000000000000000000000000000000
    assign \dm25_go_die_i \go_die_i
    sync init
  end
  process $group_243
    assign \dm25_gord1_i 30'000000000000000000000000000000
    assign \dm25_gord1_i \gord1_i
    sync init
  end
  process $group_244
    assign \dm25_gord2_i 30'000000000000000000000000000000
    assign \dm25_gord2_i \gord2_i
    sync init
  end
  process $group_245
    assign \dm25_gord3_i 30'000000000000000000000000000000
    assign \dm25_gord3_i \gord3_i
    sync init
  end
  process $group_246
    assign \dm25_gowr1_i 30'000000000000000000000000000000
    assign \dm25_gowr1_i \gowr1_i
    sync init
  end
  process $group_247
    assign \dm25_gowr2_i 30'000000000000000000000000000000
    assign \dm25_gowr2_i \gowr2_i
    sync init
  end
  process $group_248
    assign \dm26_go_die_i 30'000000000000000000000000000000
    assign \dm26_go_die_i \go_die_i
    sync init
  end
  process $group_249
    assign \dm26_gord1_i 30'000000000000000000000000000000
    assign \dm26_gord1_i \gord1_i
    sync init
  end
  process $group_250
    assign \dm26_gord2_i 30'000000000000000000000000000000
    assign \dm26_gord2_i \gord2_i
    sync init
  end
  process $group_251
    assign \dm26_gord3_i 30'000000000000000000000000000000
    assign \dm26_gord3_i \gord3_i
    sync init
  end
  process $group_252
    assign \dm26_gowr1_i 30'000000000000000000000000000000
    assign \dm26_gowr1_i \gowr1_i
    sync init
  end
  process $group_253
    assign \dm26_gowr2_i 30'000000000000000000000000000000
    assign \dm26_gowr2_i \gowr2_i
    sync init
  end
  process $group_254
    assign \dm27_go_die_i 30'000000000000000000000000000000
    assign \dm27_go_die_i \go_die_i
    sync init
  end
  process $group_255
    assign \dm27_gord1_i 30'000000000000000000000000000000
    assign \dm27_gord1_i \gord1_i
    sync init
  end
  process $group_256
    assign \dm27_gord2_i 30'000000000000000000000000000000
    assign \dm27_gord2_i \gord2_i
    sync init
  end
  process $group_257
    assign \dm27_gord3_i 30'000000000000000000000000000000
    assign \dm27_gord3_i \gord3_i
    sync init
  end
  process $group_258
    assign \dm27_gowr1_i 30'000000000000000000000000000000
    assign \dm27_gowr1_i \gowr1_i
    sync init
  end
  process $group_259
    assign \dm27_gowr2_i 30'000000000000000000000000000000
    assign \dm27_gowr2_i \gowr2_i
    sync init
  end
  process $group_260
    assign \dm28_go_die_i 30'000000000000000000000000000000
    assign \dm28_go_die_i \go_die_i
    sync init
  end
  process $group_261
    assign \dm28_gord1_i 30'000000000000000000000000000000
    assign \dm28_gord1_i \gord1_i
    sync init
  end
  process $group_262
    assign \dm28_gord2_i 30'000000000000000000000000000000
    assign \dm28_gord2_i \gord2_i
    sync init
  end
  process $group_263
    assign \dm28_gord3_i 30'000000000000000000000000000000
    assign \dm28_gord3_i \gord3_i
    sync init
  end
  process $group_264
    assign \dm28_gowr1_i 30'000000000000000000000000000000
    assign \dm28_gowr1_i \gowr1_i
    sync init
  end
  process $group_265
    assign \dm28_gowr2_i 30'000000000000000000000000000000
    assign \dm28_gowr2_i \gowr2_i
    sync init
  end
  process $group_266
    assign \dm29_go_die_i 30'000000000000000000000000000000
    assign \dm29_go_die_i \go_die_i
    sync init
  end
  process $group_267
    assign \dm29_gord1_i 30'000000000000000000000000000000
    assign \dm29_gord1_i \gord1_i
    sync init
  end
  process $group_268
    assign \dm29_gord2_i 30'000000000000000000000000000000
    assign \dm29_gord2_i \gord2_i
    sync init
  end
  process $group_269
    assign \dm29_gord3_i 30'000000000000000000000000000000
    assign \dm29_gord3_i \gord3_i
    sync init
  end
  process $group_270
    assign \dm29_gowr1_i 30'000000000000000000000000000000
    assign \dm29_gowr1_i \gowr1_i
    sync init
  end
  process $group_271
    assign \dm29_gowr2_i 30'000000000000000000000000000000
    assign \dm29_gowr2_i \gowr2_i
    sync init
  end
  process $group_272
    assign \dm0_rd_pend_i 30'000000000000000000000000000000
    assign \dm0_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_273
    assign \dm0_wr_pend_i 30'000000000000000000000000000000
    assign \dm0_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_274
    assign \dm1_rd_pend_i 30'000000000000000000000000000000
    assign \dm1_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_275
    assign \dm1_wr_pend_i 30'000000000000000000000000000000
    assign \dm1_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_276
    assign \dm2_rd_pend_i 30'000000000000000000000000000000
    assign \dm2_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_277
    assign \dm2_wr_pend_i 30'000000000000000000000000000000
    assign \dm2_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_278
    assign \dm3_rd_pend_i 30'000000000000000000000000000000
    assign \dm3_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_279
    assign \dm3_wr_pend_i 30'000000000000000000000000000000
    assign \dm3_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_280
    assign \dm4_rd_pend_i 30'000000000000000000000000000000
    assign \dm4_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_281
    assign \dm4_wr_pend_i 30'000000000000000000000000000000
    assign \dm4_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_282
    assign \dm5_rd_pend_i 30'000000000000000000000000000000
    assign \dm5_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_283
    assign \dm5_wr_pend_i 30'000000000000000000000000000000
    assign \dm5_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_284
    assign \dm6_rd_pend_i 30'000000000000000000000000000000
    assign \dm6_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_285
    assign \dm6_wr_pend_i 30'000000000000000000000000000000
    assign \dm6_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_286
    assign \dm7_rd_pend_i 30'000000000000000000000000000000
    assign \dm7_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_287
    assign \dm7_wr_pend_i 30'000000000000000000000000000000
    assign \dm7_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_288
    assign \dm8_rd_pend_i 30'000000000000000000000000000000
    assign \dm8_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_289
    assign \dm8_wr_pend_i 30'000000000000000000000000000000
    assign \dm8_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_290
    assign \dm9_rd_pend_i 30'000000000000000000000000000000
    assign \dm9_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_291
    assign \dm9_wr_pend_i 30'000000000000000000000000000000
    assign \dm9_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_292
    assign \dm10_rd_pend_i 30'000000000000000000000000000000
    assign \dm10_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_293
    assign \dm10_wr_pend_i 30'000000000000000000000000000000
    assign \dm10_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_294
    assign \dm11_rd_pend_i 30'000000000000000000000000000000
    assign \dm11_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_295
    assign \dm11_wr_pend_i 30'000000000000000000000000000000
    assign \dm11_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_296
    assign \dm12_rd_pend_i 30'000000000000000000000000000000
    assign \dm12_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_297
    assign \dm12_wr_pend_i 30'000000000000000000000000000000
    assign \dm12_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_298
    assign \dm13_rd_pend_i 30'000000000000000000000000000000
    assign \dm13_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_299
    assign \dm13_wr_pend_i 30'000000000000000000000000000000
    assign \dm13_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_300
    assign \dm14_rd_pend_i 30'000000000000000000000000000000
    assign \dm14_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_301
    assign \dm14_wr_pend_i 30'000000000000000000000000000000
    assign \dm14_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_302
    assign \dm15_rd_pend_i 30'000000000000000000000000000000
    assign \dm15_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_303
    assign \dm15_wr_pend_i 30'000000000000000000000000000000
    assign \dm15_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_304
    assign \dm16_rd_pend_i 30'000000000000000000000000000000
    assign \dm16_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_305
    assign \dm16_wr_pend_i 30'000000000000000000000000000000
    assign \dm16_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_306
    assign \dm17_rd_pend_i 30'000000000000000000000000000000
    assign \dm17_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_307
    assign \dm17_wr_pend_i 30'000000000000000000000000000000
    assign \dm17_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_308
    assign \dm18_rd_pend_i 30'000000000000000000000000000000
    assign \dm18_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_309
    assign \dm18_wr_pend_i 30'000000000000000000000000000000
    assign \dm18_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_310
    assign \dm19_rd_pend_i 30'000000000000000000000000000000
    assign \dm19_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_311
    assign \dm19_wr_pend_i 30'000000000000000000000000000000
    assign \dm19_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_312
    assign \dm20_rd_pend_i 30'000000000000000000000000000000
    assign \dm20_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_313
    assign \dm20_wr_pend_i 30'000000000000000000000000000000
    assign \dm20_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_314
    assign \dm21_rd_pend_i 30'000000000000000000000000000000
    assign \dm21_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_315
    assign \dm21_wr_pend_i 30'000000000000000000000000000000
    assign \dm21_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_316
    assign \dm22_rd_pend_i 30'000000000000000000000000000000
    assign \dm22_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_317
    assign \dm22_wr_pend_i 30'000000000000000000000000000000
    assign \dm22_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_318
    assign \dm23_rd_pend_i 30'000000000000000000000000000000
    assign \dm23_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_319
    assign \dm23_wr_pend_i 30'000000000000000000000000000000
    assign \dm23_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_320
    assign \dm24_rd_pend_i 30'000000000000000000000000000000
    assign \dm24_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_321
    assign \dm24_wr_pend_i 30'000000000000000000000000000000
    assign \dm24_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_322
    assign \dm25_rd_pend_i 30'000000000000000000000000000000
    assign \dm25_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_323
    assign \dm25_wr_pend_i 30'000000000000000000000000000000
    assign \dm25_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_324
    assign \dm26_rd_pend_i 30'000000000000000000000000000000
    assign \dm26_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_325
    assign \dm26_wr_pend_i 30'000000000000000000000000000000
    assign \dm26_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_326
    assign \dm27_rd_pend_i 30'000000000000000000000000000000
    assign \dm27_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_327
    assign \dm27_wr_pend_i 30'000000000000000000000000000000
    assign \dm27_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_328
    assign \dm28_rd_pend_i 30'000000000000000000000000000000
    assign \dm28_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_329
    assign \dm28_wr_pend_i 30'000000000000000000000000000000
    assign \dm28_wr_pend_i \wr_pend_i
    sync init
  end
  process $group_330
    assign \dm29_rd_pend_i 30'000000000000000000000000000000
    assign \dm29_rd_pend_i \rd_pend_i
    sync init
  end
  process $group_331
    assign \dm29_wr_pend_i 30'000000000000000000000000000000
    assign \dm29_wr_pend_i \wr_pend_i
    sync init
  end
end