attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0.war_l"
module \war_l
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 0 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 1 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 2 \qn
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0.raw_l"
module \raw_l
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 0 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 1 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 2 \qn
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 3 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 4 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0"
module \dm_fu0
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l \war_l
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l \raw_l
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1.war_l"
module \war_l$1
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1.raw_l"
module \raw_l$2
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1"
module \dm_fu1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$1 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$2 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2.war_l"
module \war_l$3
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2.raw_l"
module \raw_l$4
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2"
module \dm_fu2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$3 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$4 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3.war_l"
module \war_l$5
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3.raw_l"
module \raw_l$6
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3"
module \dm_fu3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$5 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$6 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4.war_l"
module \war_l$7
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4.raw_l"
module \raw_l$8
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4"
module \dm_fu4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$7 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$8 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5.war_l"
module \war_l$9
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5.raw_l"
module \raw_l$10
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5"
module \dm_fu5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$9 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$10 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6.war_l"
module \war_l$11
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6.raw_l"
module \raw_l$12
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6"
module \dm_fu6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$11 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$12 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7.war_l"
module \war_l$13
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7.raw_l"
module \raw_l$14
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 output 4 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7"
module \dm_fu7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 input 0 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 input 1 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 input 2 \load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 input 3 \stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 input 8 \load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 input 9 \stor_h_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 10 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 11 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \war_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \war_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \war_l_qn
  cell \war_l$13 \war_l
    connect \rst \rst
    connect \clk \clk
    connect \s \war_l_s
    connect \r \war_l_r
    connect \qn \war_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \raw_l_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \raw_l_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \raw_l_qn
  cell \raw_l$14 \raw_l
    connect \rst \rst
    connect \clk \clk
    connect \s \raw_l_s
    connect \r \raw_l_r
    connect \qn \raw_l_qn
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
  wire width 1 \i_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  wire width 8 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
  cell $and $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \stor_h_i
    connect \Y $2
  end
  connect $1 $2
  process $group_0
    assign \i_s 1'0
    assign \i_s $1 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
  wire width 8 \i_s_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
    connect \B \load_v_i
    connect \Y $4
  end
  process $group_1
    assign \i_s_l 8'00000000
    assign \i_s_l $4
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
  wire width 1 \i_l
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
  cell $and $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 4'1000
    connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
    connect \B \load_h_i
    connect \Y $7
  end
  connect $6 $7
  process $group_2
    assign \i_l 1'0
    assign \i_l $6 [0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
  wire width 8 \i_l_s
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
    connect \B \stor_v_i
    connect \Y $9
  end
  process $group_3
    assign \i_l_s 8'00000000
    assign \i_l_s $9
    sync init
  end
  process $group_4
    assign \war_l_s 8'00000000
    assign \war_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $not $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \load_v_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
  cell $or $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $11
    connect \Y $13
  end
  process $group_5
    assign \war_l_r 8'11111111
    assign \war_l_r $13
    sync init
  end
  process $group_6
    assign \raw_l_s 8'00000000
    assign \raw_l_s \i_s_l
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $not $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \stor_v_i
    connect \Y $15
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
    connect \B $15
    connect \Y $17
  end
  process $group_7
    assign \raw_l_r 8'11111111
    assign \raw_l_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 1 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  wire width 8 $20
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $and $21
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \war_l_qn
    connect \B \load_hit_i
    connect \Y $20
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
  cell $reduce_bool $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $20
    connect \Y $19
  end
  process $group_8
    assign \ld_hold_st_o 1'0
    assign \ld_hold_st_o $19
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 1 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  wire width 8 $24
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $and $25
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \raw_l_qn
    connect \B \stwd_hit_i
    connect \Y $24
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
  cell $reduce_bool $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A $24
    connect \Y $23
  end
  process $group_9
    assign \st_hold_ld_o 1'0
    assign \st_hold_ld_o $23
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.ldstdeps"
module \ldstdeps
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:51"
  wire width 8 input 0 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:52"
  wire width 8 input 1 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:53"
  wire width 8 input 2 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:56"
  wire width 8 input 3 \load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:58"
  wire width 8 input 4 \stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:54"
  wire width 8 input 5 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:62"
  wire width 8 output 6 \ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:64"
  wire width 8 output 7 \st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 8 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 9 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu0_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu0_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu0_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu0_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu0_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu0_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu0_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu0_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu0_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu0_stor_h_i
  cell \dm_fu0 \dm_fu0
    connect \load_hit_i \dm_fu0_load_hit_i
    connect \stwd_hit_i \dm_fu0_stwd_hit_i
    connect \load_v_i \dm_fu0_load_v_i
    connect \stor_v_i \dm_fu0_stor_v_i
    connect \issue_i \dm_fu0_issue_i
    connect \go_die_i \dm_fu0_go_die_i
    connect \ld_hold_st_o \dm_fu0_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu0_st_hold_ld_o
    connect \load_h_i \dm_fu0_load_h_i
    connect \stor_h_i \dm_fu0_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu1_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu1_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu1_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu1_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu1_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu1_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu1_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu1_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu1_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu1_stor_h_i
  cell \dm_fu1 \dm_fu1
    connect \load_hit_i \dm_fu1_load_hit_i
    connect \stwd_hit_i \dm_fu1_stwd_hit_i
    connect \load_v_i \dm_fu1_load_v_i
    connect \stor_v_i \dm_fu1_stor_v_i
    connect \issue_i \dm_fu1_issue_i
    connect \go_die_i \dm_fu1_go_die_i
    connect \ld_hold_st_o \dm_fu1_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu1_st_hold_ld_o
    connect \load_h_i \dm_fu1_load_h_i
    connect \stor_h_i \dm_fu1_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu2_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu2_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu2_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu2_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu2_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu2_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu2_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu2_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu2_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu2_stor_h_i
  cell \dm_fu2 \dm_fu2
    connect \load_hit_i \dm_fu2_load_hit_i
    connect \stwd_hit_i \dm_fu2_stwd_hit_i
    connect \load_v_i \dm_fu2_load_v_i
    connect \stor_v_i \dm_fu2_stor_v_i
    connect \issue_i \dm_fu2_issue_i
    connect \go_die_i \dm_fu2_go_die_i
    connect \ld_hold_st_o \dm_fu2_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu2_st_hold_ld_o
    connect \load_h_i \dm_fu2_load_h_i
    connect \stor_h_i \dm_fu2_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu3_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu3_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu3_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu3_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu3_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu3_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu3_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu3_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu3_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu3_stor_h_i
  cell \dm_fu3 \dm_fu3
    connect \load_hit_i \dm_fu3_load_hit_i
    connect \stwd_hit_i \dm_fu3_stwd_hit_i
    connect \load_v_i \dm_fu3_load_v_i
    connect \stor_v_i \dm_fu3_stor_v_i
    connect \issue_i \dm_fu3_issue_i
    connect \go_die_i \dm_fu3_go_die_i
    connect \ld_hold_st_o \dm_fu3_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu3_st_hold_ld_o
    connect \load_h_i \dm_fu3_load_h_i
    connect \stor_h_i \dm_fu3_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu4_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu4_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu4_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu4_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu4_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu4_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu4_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu4_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu4_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu4_stor_h_i
  cell \dm_fu4 \dm_fu4
    connect \load_hit_i \dm_fu4_load_hit_i
    connect \stwd_hit_i \dm_fu4_stwd_hit_i
    connect \load_v_i \dm_fu4_load_v_i
    connect \stor_v_i \dm_fu4_stor_v_i
    connect \issue_i \dm_fu4_issue_i
    connect \go_die_i \dm_fu4_go_die_i
    connect \ld_hold_st_o \dm_fu4_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu4_st_hold_ld_o
    connect \load_h_i \dm_fu4_load_h_i
    connect \stor_h_i \dm_fu4_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu5_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu5_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu5_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu5_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu5_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu5_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu5_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu5_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu5_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu5_stor_h_i
  cell \dm_fu5 \dm_fu5
    connect \load_hit_i \dm_fu5_load_hit_i
    connect \stwd_hit_i \dm_fu5_stwd_hit_i
    connect \load_v_i \dm_fu5_load_v_i
    connect \stor_v_i \dm_fu5_stor_v_i
    connect \issue_i \dm_fu5_issue_i
    connect \go_die_i \dm_fu5_go_die_i
    connect \ld_hold_st_o \dm_fu5_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu5_st_hold_ld_o
    connect \load_h_i \dm_fu5_load_h_i
    connect \stor_h_i \dm_fu5_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu6_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu6_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu6_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu6_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu6_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu6_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu6_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu6_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu6_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu6_stor_h_i
  cell \dm_fu6 \dm_fu6
    connect \load_hit_i \dm_fu6_load_hit_i
    connect \stwd_hit_i \dm_fu6_stwd_hit_i
    connect \load_v_i \dm_fu6_load_v_i
    connect \stor_v_i \dm_fu6_stor_v_i
    connect \issue_i \dm_fu6_issue_i
    connect \go_die_i \dm_fu6_go_die_i
    connect \ld_hold_st_o \dm_fu6_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu6_st_hold_ld_o
    connect \load_h_i \dm_fu6_load_h_i
    connect \stor_h_i \dm_fu6_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
  wire width 8 \dm_fu7_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
  wire width 8 \dm_fu7_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
  wire width 8 \dm_fu7_load_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
  wire width 8 \dm_fu7_stor_v_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
  wire width 1 \dm_fu7_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
  wire width 1 \dm_fu7_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
  wire width 1 \dm_fu7_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
  wire width 1 \dm_fu7_st_hold_ld_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
  wire width 1 \dm_fu7_load_h_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
  wire width 1 \dm_fu7_stor_h_i
  cell \dm_fu7 \dm_fu7
    connect \load_hit_i \dm_fu7_load_hit_i
    connect \stwd_hit_i \dm_fu7_stwd_hit_i
    connect \load_v_i \dm_fu7_load_v_i
    connect \stor_v_i \dm_fu7_stor_v_i
    connect \issue_i \dm_fu7_issue_i
    connect \go_die_i \dm_fu7_go_die_i
    connect \ld_hold_st_o \dm_fu7_ld_hold_st_o
    connect \st_hold_ld_o \dm_fu7_st_hold_ld_o
    connect \load_h_i \dm_fu7_load_h_i
    connect \stor_h_i \dm_fu7_stor_h_i
    connect \rst \rst
    connect \clk \clk
  end
  process $group_0
    assign \dm_fu0_load_hit_i 8'00000000
    assign \dm_fu0_load_hit_i \load_hit_i
    sync init
  end
  process $group_1
    assign \dm_fu0_stwd_hit_i 8'00000000
    assign \dm_fu0_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_2
    assign \dm_fu0_load_v_i 8'00000000
    assign \dm_fu0_load_v_i \ld_pend_i
    sync init
  end
  process $group_3
    assign \dm_fu0_stor_v_i 8'00000000
    assign \dm_fu0_stor_v_i \st_pend_i
    sync init
  end
  process $group_4
    assign \dm_fu1_load_hit_i 8'00000000
    assign \dm_fu1_load_hit_i \load_hit_i
    sync init
  end
  process $group_5
    assign \dm_fu1_stwd_hit_i 8'00000000
    assign \dm_fu1_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_6
    assign \dm_fu1_load_v_i 8'00000000
    assign \dm_fu1_load_v_i \ld_pend_i
    sync init
  end
  process $group_7
    assign \dm_fu1_stor_v_i 8'00000000
    assign \dm_fu1_stor_v_i \st_pend_i
    sync init
  end
  process $group_8
    assign \dm_fu2_load_hit_i 8'00000000
    assign \dm_fu2_load_hit_i \load_hit_i
    sync init
  end
  process $group_9
    assign \dm_fu2_stwd_hit_i 8'00000000
    assign \dm_fu2_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_10
    assign \dm_fu2_load_v_i 8'00000000
    assign \dm_fu2_load_v_i \ld_pend_i
    sync init
  end
  process $group_11
    assign \dm_fu2_stor_v_i 8'00000000
    assign \dm_fu2_stor_v_i \st_pend_i
    sync init
  end
  process $group_12
    assign \dm_fu3_load_hit_i 8'00000000
    assign \dm_fu3_load_hit_i \load_hit_i
    sync init
  end
  process $group_13
    assign \dm_fu3_stwd_hit_i 8'00000000
    assign \dm_fu3_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_14
    assign \dm_fu3_load_v_i 8'00000000
    assign \dm_fu3_load_v_i \ld_pend_i
    sync init
  end
  process $group_15
    assign \dm_fu3_stor_v_i 8'00000000
    assign \dm_fu3_stor_v_i \st_pend_i
    sync init
  end
  process $group_16
    assign \dm_fu4_load_hit_i 8'00000000
    assign \dm_fu4_load_hit_i \load_hit_i
    sync init
  end
  process $group_17
    assign \dm_fu4_stwd_hit_i 8'00000000
    assign \dm_fu4_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_18
    assign \dm_fu4_load_v_i 8'00000000
    assign \dm_fu4_load_v_i \ld_pend_i
    sync init
  end
  process $group_19
    assign \dm_fu4_stor_v_i 8'00000000
    assign \dm_fu4_stor_v_i \st_pend_i
    sync init
  end
  process $group_20
    assign \dm_fu5_load_hit_i 8'00000000
    assign \dm_fu5_load_hit_i \load_hit_i
    sync init
  end
  process $group_21
    assign \dm_fu5_stwd_hit_i 8'00000000
    assign \dm_fu5_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_22
    assign \dm_fu5_load_v_i 8'00000000
    assign \dm_fu5_load_v_i \ld_pend_i
    sync init
  end
  process $group_23
    assign \dm_fu5_stor_v_i 8'00000000
    assign \dm_fu5_stor_v_i \st_pend_i
    sync init
  end
  process $group_24
    assign \dm_fu6_load_hit_i 8'00000000
    assign \dm_fu6_load_hit_i \load_hit_i
    sync init
  end
  process $group_25
    assign \dm_fu6_stwd_hit_i 8'00000000
    assign \dm_fu6_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_26
    assign \dm_fu6_load_v_i 8'00000000
    assign \dm_fu6_load_v_i \ld_pend_i
    sync init
  end
  process $group_27
    assign \dm_fu6_stor_v_i 8'00000000
    assign \dm_fu6_stor_v_i \st_pend_i
    sync init
  end
  process $group_28
    assign \dm_fu7_load_hit_i 8'00000000
    assign \dm_fu7_load_hit_i \load_hit_i
    sync init
  end
  process $group_29
    assign \dm_fu7_stwd_hit_i 8'00000000
    assign \dm_fu7_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_30
    assign \dm_fu7_load_v_i 8'00000000
    assign \dm_fu7_load_v_i \ld_pend_i
    sync init
  end
  process $group_31
    assign \dm_fu7_stor_v_i 8'00000000
    assign \dm_fu7_stor_v_i \st_pend_i
    sync init
  end
  process $group_32
    assign \dm_fu0_issue_i 1'0
    assign \dm_fu1_issue_i 1'0
    assign \dm_fu2_issue_i 1'0
    assign \dm_fu3_issue_i 1'0
    assign \dm_fu4_issue_i 1'0
    assign \dm_fu5_issue_i 1'0
    assign \dm_fu6_issue_i 1'0
    assign \dm_fu7_issue_i 1'0
    assign { \dm_fu7_issue_i \dm_fu6_issue_i \dm_fu5_issue_i \dm_fu4_issue_i \dm_fu3_issue_i \dm_fu2_issue_i \dm_fu1_issue_i \dm_fu0_issue_i } \issue_i
    sync init
  end
  process $group_40
    assign \dm_fu0_go_die_i 1'0
    assign \dm_fu1_go_die_i 1'0
    assign \dm_fu2_go_die_i 1'0
    assign \dm_fu3_go_die_i 1'0
    assign \dm_fu4_go_die_i 1'0
    assign \dm_fu5_go_die_i 1'0
    assign \dm_fu6_go_die_i 1'0
    assign \dm_fu7_go_die_i 1'0
    assign { \dm_fu7_go_die_i \dm_fu6_go_die_i \dm_fu5_go_die_i \dm_fu4_go_die_i \dm_fu3_go_die_i \dm_fu2_go_die_i \dm_fu1_go_die_i \dm_fu0_go_die_i } \go_die_i
    sync init
  end
  process $group_48
    assign \ld_hold_st_o 8'00000000
    assign \ld_hold_st_o { \dm_fu7_ld_hold_st_o \dm_fu6_ld_hold_st_o \dm_fu5_ld_hold_st_o \dm_fu4_ld_hold_st_o \dm_fu3_ld_hold_st_o \dm_fu2_ld_hold_st_o \dm_fu1_ld_hold_st_o \dm_fu0_ld_hold_st_o }
    sync init
  end
  process $group_49
    assign \st_hold_ld_o 8'00000000
    assign \st_hold_ld_o { \dm_fu7_st_hold_ld_o \dm_fu6_st_hold_ld_o \dm_fu5_st_hold_ld_o \dm_fu4_st_hold_ld_o \dm_fu3_st_hold_ld_o \dm_fu2_st_hold_ld_o \dm_fu1_st_hold_ld_o \dm_fu0_st_hold_ld_o }
    sync init
  end
  process $group_50
    assign \dm_fu0_load_h_i 1'0
    assign \dm_fu1_load_h_i 1'0
    assign \dm_fu2_load_h_i 1'0
    assign \dm_fu3_load_h_i 1'0
    assign \dm_fu4_load_h_i 1'0
    assign \dm_fu5_load_h_i 1'0
    assign \dm_fu6_load_h_i 1'0
    assign \dm_fu7_load_h_i 1'0
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
    sync init
  end
  process $group_58
    assign \dm_fu0_stor_h_i 1'0
    assign \dm_fu1_stor_h_i 1'0
    assign \dm_fu2_stor_h_i 1'0
    assign \dm_fu3_stor_h_i 1'0
    assign \dm_fu4_stor_h_i 1'0
    assign \dm_fu5_stor_h_i 1'0
    assign \dm_fu6_stor_h_i 1'0
    assign \dm_fu7_stor_h_i 1'0
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm0.st_c"
module \st_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm0.ld_c"
module \ld_c
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm0"
module \dm0
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'11111110
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'11111110
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm1.st_c"
module \st_c$15
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm1.ld_c"
module \ld_c$16
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm1"
module \dm1
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c$15 \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c$16 \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'11111101
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'11111101
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm2.st_c"
module \st_c$17
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm2.ld_c"
module \ld_c$18
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm2"
module \dm2
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c$17 \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c$18 \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'11111011
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'11111011
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm3.st_c"
module \st_c$19
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm3.ld_c"
module \ld_c$20
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm3"
module \dm3
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c$19 \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c$20 \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'11110111
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'11110111
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm4.st_c"
module \st_c$21
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm4.ld_c"
module \ld_c$22
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm4"
module \dm4
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c$21 \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c$22 \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'11101111
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'11101111
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm5.st_c"
module \st_c$23
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm5.ld_c"
module \ld_c$24
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm5"
module \dm5
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c$23 \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c$24 \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'11011111
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'11011111
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm6.st_c"
module \st_c$25
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm6.ld_c"
module \ld_c$26
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm6"
module \dm6
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 output 2 \st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 output 3 \ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 input 4 \issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 input 5 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 input 6 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 input 7 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 input 8 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 input 9 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \st_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
  cell \st_c$25 \st_c
    connect \rst \rst
    connect \clk \clk
    connect \s \st_c_s
    connect \r \st_c_r
    connect \qlq \st_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 \ld_c_s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
  cell \ld_c$26 \ld_c
    connect \rst \rst
    connect \clk \clk
    connect \s \ld_c_s
    connect \r \ld_c_r
    connect \qlq \ld_c_qlq
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
  cell $and $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 8 $4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $5
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \st_pend_i
    connect \Y $4
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  cell $and $7
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $4
    connect \B 8'10111111
    connect \Y $6
  end
  connect $3 $6
  process $group_0
    assign \st_c_s 8'00000000
    assign \st_c_s $1
    assign \st_c_s $3 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  cell $and $9
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $8
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $10
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \B \ld_pend_i
    connect \Y $11
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  wire width 9 $13
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
  cell $and $14
    parameter \A_SIGNED 1'1
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'1
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1001
    connect \A $11
    connect \B 8'10111111
    connect \Y $13
  end
  connect $10 $13
  process $group_1
    assign \ld_c_s 8'00000000
    assign \ld_c_s $8
    assign \ld_c_s $10 [7:0]
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_ld_i
    connect \B \go_die_i
    connect \Y $15
  end
  process $group_2
    assign \ld_c_r 8'11111111
    assign \ld_c_r $15
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \go_st_i
    connect \B \go_die_i
    connect \Y $17
  end
  process $group_3
    assign \st_c_r 8'11111111
    assign \st_c_r $17
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $19
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $not $20
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $19
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  wire width 8 $21
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
  cell $and $22
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \st_c_qlq
    connect \B $19
    connect \Y $21
  end
  process $group_4
    assign \st_wait_o 8'00000000
    assign \st_wait_o $21
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $not $24
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \issue_i
    connect \Y $23
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  cell $and $26
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \ld_c_qlq
    connect \B $23
    connect \Y $25
  end
  process $group_5
    assign \ld_wait_o 8'00000000
    assign \ld_wait_o $25
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm7.st_c"
module \st_c$27
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \B \q_int
    connect \Y $15
  end
  process $group_3
    assign \qlq 8'00000000
    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm7.ld_c"
module \ld_c$28
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 0 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 1 \clk
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
  wire width 8 input 2 \s
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 input 3 \r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 output 4 \qlq
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  wire width 8 \q_int$next
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $1
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $not $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $1
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $3
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $and $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $1
    connect \Y $3
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  wire width 8 $5
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  cell $or $6
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $3
    connect \B \s
    connect \Y $5
  end
  process $group_0
    assign \q_int$next \q_int
    assign \q_int$next $5
    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
    switch \rst
      case 1'1
        assign \q_int$next 8'00000000
    end
    sync init
      update \q_int 8'00000000
    sync posedge \clk
      update \q_int \q_int$next
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
  wire width 8 \q
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $7
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \r
    connect \Y $7
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $9
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $and $10
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q_int
    connect \B $7
    connect \Y $9
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  wire width 8 $11
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  cell $or $12
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A $9
    connect \B \s
    connect \Y $11
  end
  process $group_1
    assign \q 8'00000000
    assign \q $11
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
  wire width 8 \qn
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  wire width 8 $13
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
  cell $not $14
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
    connect \A \q
    connect \Y $13
  end
  process $group_2
    assign \qn 8'00000000
    assign \qn $13
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
  cell $or $16
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 4'1000
    parameter \Y_WIDTH 4'1000
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    assign \qlq $15
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.dm7"
module \dm7
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  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
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  wire width 8 \st_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \st_c_qlq
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    connect \rst \rst
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  end
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
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  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
  wire width 8 \ld_c_r
  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  wire width 8 \ld_c_qlq
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  cell $and $2
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
  wire width 9 $6
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    parameter \Y_WIDTH 4'1001
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    assign \st_c_s 8'00000000
    assign \st_c_s $1
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    sync init
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
  wire width 8 $8
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
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    assign \ld_c_s 8'00000000
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    sync init
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
  wire width 8 $15
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
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    assign \ld_c_r 8'11111111
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    sync init
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  wire width 8 $17
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
  cell $or $18
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    assign \st_c_r 8'11111111
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    sync init
  end
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
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    parameter \B_SIGNED 1'0
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    parameter \Y_WIDTH 4'1000
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    assign \st_wait_o 8'00000000
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    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $23
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
  wire width 8 $25
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    connect \A \ld_c_qlq
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    sync init
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x0"
module \fur_x0
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
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  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $reduce_bool $3
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    connect \A \ld_pend_i
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $not $4
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    sync init
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \st_pend_i
    connect \Y $6
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
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    connect \A $6
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  process $group_1
    assign \loadable_o 1'0
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    sync init
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x1"
module \fur_x1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $reduce_bool $7
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    parameter \A_WIDTH 4'1000
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    connect \A \st_pend_i
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
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    connect \A $6
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  process $group_1
    assign \loadable_o 1'0
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    sync init
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x2"
module \fur_x2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $reduce_bool $7
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    connect \A \st_pend_i
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x3"
module \fur_x3
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x4"
module \fur_x4
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
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  process $group_1
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    assign \loadable_o $5
    sync init
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x5"
module \fur_x5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 output 1 \loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 input 2 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 input 3 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \ld_pend_i
    connect \Y $2
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
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  process $group_0
    assign \storable_o 1'0
    assign \storable_o $1
    sync init
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \st_pend_i
    connect \Y $6
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
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  process $group_1
    assign \loadable_o 1'0
    assign \loadable_o $5
    sync init
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x6"
module \fur_x6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 output 1 \loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 input 2 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 input 3 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \ld_pend_i
    connect \Y $2
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
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  process $group_0
    assign \storable_o 1'0
    assign \storable_o $1
    sync init
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \st_pend_i
    connect \Y $6
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
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  process $group_1
    assign \loadable_o 1'0
    assign \loadable_o $5
    sync init
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end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps.fur_x7"
module \fur_x7
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 output 1 \loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 input 2 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 input 3 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $1
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  wire width 1 $2
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $reduce_bool $3
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \ld_pend_i
    connect \Y $2
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  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
  cell $not $4
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $2
    connect \Y $1
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  process $group_0
    assign \storable_o 1'0
    assign \storable_o $1
    sync init
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $5
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  wire width 1 $6
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $reduce_bool $7
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 4'1000
    parameter \Y_WIDTH 1'1
    connect \A \st_pend_i
    connect \Y $6
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
  cell $not $8
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A $6
    connect \Y $5
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  process $group_1
    assign \loadable_o 1'0
    assign \loadable_o $5
    sync init
  end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.fumemdeps"
module \fumemdeps
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:30"
  wire width 8 output 0 \storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:31"
  wire width 8 output 1 \loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:22"
  wire width 8 input 2 \ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:21"
  wire width 8 input 3 \st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:26"
  wire width 8 input 4 \go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:25"
  wire width 8 input 5 \go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:27"
  wire width 8 input 6 \go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:23"
  wire width 8 input 7 \issue_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 8 \rst
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 9 \clk
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm0_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm0_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm0_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm0_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm0_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm0_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm0_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm0_ld_pend_i
  cell \dm0 \dm0
    connect \rst \rst
    connect \clk \clk
    connect \st_wait_o \dm0_st_wait_o
    connect \ld_wait_o \dm0_ld_wait_o
    connect \issue_i \dm0_issue_i
    connect \go_st_i \dm0_go_st_i
    connect \go_ld_i \dm0_go_ld_i
    connect \go_die_i \dm0_go_die_i
    connect \st_pend_i \dm0_st_pend_i
    connect \ld_pend_i \dm0_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm1_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm1_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm1_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm1_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm1_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm1_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm1_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm1_ld_pend_i
  cell \dm1 \dm1
    connect \rst \rst
    connect \clk \clk
    connect \st_wait_o \dm1_st_wait_o
    connect \ld_wait_o \dm1_ld_wait_o
    connect \issue_i \dm1_issue_i
    connect \go_st_i \dm1_go_st_i
    connect \go_ld_i \dm1_go_ld_i
    connect \go_die_i \dm1_go_die_i
    connect \st_pend_i \dm1_st_pend_i
    connect \ld_pend_i \dm1_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm2_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm2_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm2_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm2_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm2_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm2_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm2_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm2_ld_pend_i
  cell \dm2 \dm2
    connect \rst \rst
    connect \clk \clk
    connect \st_wait_o \dm2_st_wait_o
    connect \ld_wait_o \dm2_ld_wait_o
    connect \issue_i \dm2_issue_i
    connect \go_st_i \dm2_go_st_i
    connect \go_ld_i \dm2_go_ld_i
    connect \go_die_i \dm2_go_die_i
    connect \st_pend_i \dm2_st_pend_i
    connect \ld_pend_i \dm2_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm3_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm3_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm3_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm3_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm3_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm3_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm3_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm3_ld_pend_i
  cell \dm3 \dm3
    connect \rst \rst
    connect \clk \clk
    connect \st_wait_o \dm3_st_wait_o
    connect \ld_wait_o \dm3_ld_wait_o
    connect \issue_i \dm3_issue_i
    connect \go_st_i \dm3_go_st_i
    connect \go_ld_i \dm3_go_ld_i
    connect \go_die_i \dm3_go_die_i
    connect \st_pend_i \dm3_st_pend_i
    connect \ld_pend_i \dm3_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm4_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm4_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm4_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm4_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm4_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm4_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm4_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm4_ld_pend_i
  cell \dm4 \dm4
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    connect \clk \clk
    connect \st_wait_o \dm4_st_wait_o
    connect \ld_wait_o \dm4_ld_wait_o
    connect \issue_i \dm4_issue_i
    connect \go_st_i \dm4_go_st_i
    connect \go_ld_i \dm4_go_ld_i
    connect \go_die_i \dm4_go_die_i
    connect \st_pend_i \dm4_st_pend_i
    connect \ld_pend_i \dm4_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm5_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm5_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm5_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm5_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm5_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm5_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm5_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm5_ld_pend_i
  cell \dm5 \dm5
    connect \rst \rst
    connect \clk \clk
    connect \st_wait_o \dm5_st_wait_o
    connect \ld_wait_o \dm5_ld_wait_o
    connect \issue_i \dm5_issue_i
    connect \go_st_i \dm5_go_st_i
    connect \go_ld_i \dm5_go_ld_i
    connect \go_die_i \dm5_go_die_i
    connect \st_pend_i \dm5_st_pend_i
    connect \ld_pend_i \dm5_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm6_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm6_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm6_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm6_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm6_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm6_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm6_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm6_ld_pend_i
  cell \dm6 \dm6
    connect \rst \rst
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    connect \ld_wait_o \dm6_ld_wait_o
    connect \issue_i \dm6_issue_i
    connect \go_st_i \dm6_go_st_i
    connect \go_ld_i \dm6_go_ld_i
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    connect \st_pend_i \dm6_st_pend_i
    connect \ld_pend_i \dm6_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
  wire width 8 \dm7_st_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
  wire width 8 \dm7_ld_wait_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
  wire width 8 \dm7_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
  wire width 8 \dm7_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
  wire width 8 \dm7_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
  wire width 8 \dm7_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
  wire width 8 \dm7_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
  wire width 8 \dm7_ld_pend_i
  cell \dm7 \dm7
    connect \rst \rst
    connect \clk \clk
    connect \st_wait_o \dm7_st_wait_o
    connect \ld_wait_o \dm7_ld_wait_o
    connect \issue_i \dm7_issue_i
    connect \go_st_i \dm7_go_st_i
    connect \go_ld_i \dm7_go_ld_i
    connect \go_die_i \dm7_go_die_i
    connect \st_pend_i \dm7_st_pend_i
    connect \ld_pend_i \dm7_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x0_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x0_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x0_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x0_ld_pend_i
  cell \fur_x0 \fur_x0
    connect \storable_o \fur_x0_storable_o
    connect \loadable_o \fur_x0_loadable_o
    connect \st_pend_i \fur_x0_st_pend_i
    connect \ld_pend_i \fur_x0_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x1_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x1_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x1_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x1_ld_pend_i
  cell \fur_x1 \fur_x1
    connect \storable_o \fur_x1_storable_o
    connect \loadable_o \fur_x1_loadable_o
    connect \st_pend_i \fur_x1_st_pend_i
    connect \ld_pend_i \fur_x1_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x2_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x2_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x2_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x2_ld_pend_i
  cell \fur_x2 \fur_x2
    connect \storable_o \fur_x2_storable_o
    connect \loadable_o \fur_x2_loadable_o
    connect \st_pend_i \fur_x2_st_pend_i
    connect \ld_pend_i \fur_x2_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x3_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x3_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x3_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x3_ld_pend_i
  cell \fur_x3 \fur_x3
    connect \storable_o \fur_x3_storable_o
    connect \loadable_o \fur_x3_loadable_o
    connect \st_pend_i \fur_x3_st_pend_i
    connect \ld_pend_i \fur_x3_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x4_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x4_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x4_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x4_ld_pend_i
  cell \fur_x4 \fur_x4
    connect \storable_o \fur_x4_storable_o
    connect \loadable_o \fur_x4_loadable_o
    connect \st_pend_i \fur_x4_st_pend_i
    connect \ld_pend_i \fur_x4_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x5_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x5_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x5_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x5_ld_pend_i
  cell \fur_x5 \fur_x5
    connect \storable_o \fur_x5_storable_o
    connect \loadable_o \fur_x5_loadable_o
    connect \st_pend_i \fur_x5_st_pend_i
    connect \ld_pend_i \fur_x5_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x6_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x6_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x6_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x6_ld_pend_i
  cell \fur_x6 \fur_x6
    connect \storable_o \fur_x6_storable_o
    connect \loadable_o \fur_x6_loadable_o
    connect \st_pend_i \fur_x6_st_pend_i
    connect \ld_pend_i \fur_x6_ld_pend_i
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
  wire width 1 \fur_x7_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
  wire width 1 \fur_x7_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
  wire width 8 \fur_x7_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
  wire width 8 \fur_x7_ld_pend_i
  cell \fur_x7 \fur_x7
    connect \storable_o \fur_x7_storable_o
    connect \loadable_o \fur_x7_loadable_o
    connect \st_pend_i \fur_x7_st_pend_i
    connect \ld_pend_i \fur_x7_ld_pend_i
  end
  process $group_0
    assign \storable_o 8'00000000
    assign \storable_o { \fur_x7_storable_o \fur_x6_storable_o \fur_x5_storable_o \fur_x4_storable_o \fur_x3_storable_o \fur_x2_storable_o \fur_x1_storable_o \fur_x0_storable_o }
    sync init
  end
  process $group_1
    assign \loadable_o 8'00000000
    assign \loadable_o { \fur_x7_loadable_o \fur_x6_loadable_o \fur_x5_loadable_o \fur_x4_loadable_o \fur_x3_loadable_o \fur_x2_loadable_o \fur_x1_loadable_o \fur_x0_loadable_o }
    sync init
  end
  process $group_2
    assign \fur_x0_st_pend_i 8'00000000
    assign \fur_x0_st_pend_i \dm0_st_wait_o
    sync init
  end
  process $group_3
    assign \fur_x0_ld_pend_i 8'00000000
    assign \fur_x0_ld_pend_i \dm0_ld_wait_o
    sync init
  end
  process $group_4
    assign \fur_x1_st_pend_i 8'00000000
    assign \fur_x1_st_pend_i \dm1_st_wait_o
    sync init
  end
  process $group_5
    assign \fur_x1_ld_pend_i 8'00000000
    assign \fur_x1_ld_pend_i \dm1_ld_wait_o
    sync init
  end
  process $group_6
    assign \fur_x2_st_pend_i 8'00000000
    assign \fur_x2_st_pend_i \dm2_st_wait_o
    sync init
  end
  process $group_7
    assign \fur_x2_ld_pend_i 8'00000000
    assign \fur_x2_ld_pend_i \dm2_ld_wait_o
    sync init
  end
  process $group_8
    assign \fur_x3_st_pend_i 8'00000000
    assign \fur_x3_st_pend_i \dm3_st_wait_o
    sync init
  end
  process $group_9
    assign \fur_x3_ld_pend_i 8'00000000
    assign \fur_x3_ld_pend_i \dm3_ld_wait_o
    sync init
  end
  process $group_10
    assign \fur_x4_st_pend_i 8'00000000
    assign \fur_x4_st_pend_i \dm4_st_wait_o
    sync init
  end
  process $group_11
    assign \fur_x4_ld_pend_i 8'00000000
    assign \fur_x4_ld_pend_i \dm4_ld_wait_o
    sync init
  end
  process $group_12
    assign \fur_x5_st_pend_i 8'00000000
    assign \fur_x5_st_pend_i \dm5_st_wait_o
    sync init
  end
  process $group_13
    assign \fur_x5_ld_pend_i 8'00000000
    assign \fur_x5_ld_pend_i \dm5_ld_wait_o
    sync init
  end
  process $group_14
    assign \fur_x6_st_pend_i 8'00000000
    assign \fur_x6_st_pend_i \dm6_st_wait_o
    sync init
  end
  process $group_15
    assign \fur_x6_ld_pend_i 8'00000000
    assign \fur_x6_ld_pend_i \dm6_ld_wait_o
    sync init
  end
  process $group_16
    assign \fur_x7_st_pend_i 8'00000000
    assign \fur_x7_st_pend_i \dm7_st_wait_o
    sync init
  end
  process $group_17
    assign \fur_x7_ld_pend_i 8'00000000
    assign \fur_x7_ld_pend_i \dm7_ld_wait_o
    sync init
  end
  process $group_18
    assign \dm0_issue_i 8'00000000
    assign \dm1_issue_i 8'00000000
    assign \dm2_issue_i 8'00000000
    assign \dm3_issue_i 8'00000000
    assign \dm4_issue_i 8'00000000
    assign \dm5_issue_i 8'00000000
    assign \dm6_issue_i 8'00000000
    assign \dm7_issue_i 8'00000000
    assign { \dm7_issue_i [0] \dm6_issue_i [0] \dm5_issue_i [0] \dm4_issue_i [0] \dm3_issue_i [0] \dm2_issue_i [0] \dm1_issue_i [0] \dm0_issue_i [0] } \issue_i
    assign { \dm7_issue_i [1] \dm6_issue_i [1] \dm5_issue_i [1] \dm4_issue_i [1] \dm3_issue_i [1] \dm2_issue_i [1] \dm1_issue_i [1] \dm0_issue_i [1] } \issue_i
    assign { \dm7_issue_i [2] \dm6_issue_i [2] \dm5_issue_i [2] \dm4_issue_i [2] \dm3_issue_i [2] \dm2_issue_i [2] \dm1_issue_i [2] \dm0_issue_i [2] } \issue_i
    assign { \dm7_issue_i [3] \dm6_issue_i [3] \dm5_issue_i [3] \dm4_issue_i [3] \dm3_issue_i [3] \dm2_issue_i [3] \dm1_issue_i [3] \dm0_issue_i [3] } \issue_i
    assign { \dm7_issue_i [4] \dm6_issue_i [4] \dm5_issue_i [4] \dm4_issue_i [4] \dm3_issue_i [4] \dm2_issue_i [4] \dm1_issue_i [4] \dm0_issue_i [4] } \issue_i
    assign { \dm7_issue_i [5] \dm6_issue_i [5] \dm5_issue_i [5] \dm4_issue_i [5] \dm3_issue_i [5] \dm2_issue_i [5] \dm1_issue_i [5] \dm0_issue_i [5] } \issue_i
    assign { \dm7_issue_i [6] \dm6_issue_i [6] \dm5_issue_i [6] \dm4_issue_i [6] \dm3_issue_i [6] \dm2_issue_i [6] \dm1_issue_i [6] \dm0_issue_i [6] } \issue_i
    assign { \dm7_issue_i [7] \dm6_issue_i [7] \dm5_issue_i [7] \dm4_issue_i [7] \dm3_issue_i [7] \dm2_issue_i [7] \dm1_issue_i [7] \dm0_issue_i [7] } \issue_i
    sync init
  end
  process $group_26
    assign \dm0_go_st_i 8'00000000
    assign \dm0_go_st_i \go_st_i
    sync init
  end
  process $group_27
    assign \dm0_go_ld_i 8'00000000
    assign \dm0_go_ld_i \go_ld_i
    sync init
  end
  process $group_28
    assign \dm0_go_die_i 8'00000000
    assign \dm0_go_die_i \go_die_i
    sync init
  end
  process $group_29
    assign \dm1_go_st_i 8'00000000
    assign \dm1_go_st_i \go_st_i
    sync init
  end
  process $group_30
    assign \dm1_go_ld_i 8'00000000
    assign \dm1_go_ld_i \go_ld_i
    sync init
  end
  process $group_31
    assign \dm1_go_die_i 8'00000000
    assign \dm1_go_die_i \go_die_i
    sync init
  end
  process $group_32
    assign \dm2_go_st_i 8'00000000
    assign \dm2_go_st_i \go_st_i
    sync init
  end
  process $group_33
    assign \dm2_go_ld_i 8'00000000
    assign \dm2_go_ld_i \go_ld_i
    sync init
  end
  process $group_34
    assign \dm2_go_die_i 8'00000000
    assign \dm2_go_die_i \go_die_i
    sync init
  end
  process $group_35
    assign \dm3_go_st_i 8'00000000
    assign \dm3_go_st_i \go_st_i
    sync init
  end
  process $group_36
    assign \dm3_go_ld_i 8'00000000
    assign \dm3_go_ld_i \go_ld_i
    sync init
  end
  process $group_37
    assign \dm3_go_die_i 8'00000000
    assign \dm3_go_die_i \go_die_i
    sync init
  end
  process $group_38
    assign \dm4_go_st_i 8'00000000
    assign \dm4_go_st_i \go_st_i
    sync init
  end
  process $group_39
    assign \dm4_go_ld_i 8'00000000
    assign \dm4_go_ld_i \go_ld_i
    sync init
  end
  process $group_40
    assign \dm4_go_die_i 8'00000000
    assign \dm4_go_die_i \go_die_i
    sync init
  end
  process $group_41
    assign \dm5_go_st_i 8'00000000
    assign \dm5_go_st_i \go_st_i
    sync init
  end
  process $group_42
    assign \dm5_go_ld_i 8'00000000
    assign \dm5_go_ld_i \go_ld_i
    sync init
  end
  process $group_43
    assign \dm5_go_die_i 8'00000000
    assign \dm5_go_die_i \go_die_i
    sync init
  end
  process $group_44
    assign \dm6_go_st_i 8'00000000
    assign \dm6_go_st_i \go_st_i
    sync init
  end
  process $group_45
    assign \dm6_go_ld_i 8'00000000
    assign \dm6_go_ld_i \go_ld_i
    sync init
  end
  process $group_46
    assign \dm6_go_die_i 8'00000000
    assign \dm6_go_die_i \go_die_i
    sync init
  end
  process $group_47
    assign \dm7_go_st_i 8'00000000
    assign \dm7_go_st_i \go_st_i
    sync init
  end
  process $group_48
    assign \dm7_go_ld_i 8'00000000
    assign \dm7_go_ld_i \go_ld_i
    sync init
  end
  process $group_49
    assign \dm7_go_die_i 8'00000000
    assign \dm7_go_die_i \go_die_i
    sync init
  end
  process $group_50
    assign \dm0_st_pend_i 8'00000000
    assign \dm0_st_pend_i \st_pend_i
    sync init
  end
  process $group_51
    assign \dm0_ld_pend_i 8'00000000
    assign \dm0_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_52
    assign \dm1_st_pend_i 8'00000000
    assign \dm1_st_pend_i \st_pend_i
    sync init
  end
  process $group_53
    assign \dm1_ld_pend_i 8'00000000
    assign \dm1_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_54
    assign \dm2_st_pend_i 8'00000000
    assign \dm2_st_pend_i \st_pend_i
    sync init
  end
  process $group_55
    assign \dm2_ld_pend_i 8'00000000
    assign \dm2_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_56
    assign \dm3_st_pend_i 8'00000000
    assign \dm3_st_pend_i \st_pend_i
    sync init
  end
  process $group_57
    assign \dm3_ld_pend_i 8'00000000
    assign \dm3_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_58
    assign \dm4_st_pend_i 8'00000000
    assign \dm4_st_pend_i \st_pend_i
    sync init
  end
  process $group_59
    assign \dm4_ld_pend_i 8'00000000
    assign \dm4_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_60
    assign \dm5_st_pend_i 8'00000000
    assign \dm5_st_pend_i \st_pend_i
    sync init
  end
  process $group_61
    assign \dm5_ld_pend_i 8'00000000
    assign \dm5_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_62
    assign \dm6_st_pend_i 8'00000000
    assign \dm6_st_pend_i \st_pend_i
    sync init
  end
  process $group_63
    assign \dm6_ld_pend_i 8'00000000
    assign \dm6_ld_pend_i \ld_pend_i
    sync init
  end
  process $group_64
    assign \dm7_st_pend_i 8'00000000
    assign \dm7_st_pend_i \st_pend_i
    sync init
  end
  process $group_65
    assign \dm7_ld_pend_i 8'00000000
    assign \dm7_ld_pend_i \ld_pend_i
    sync init
  end
end
attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "test_mem_fus"
module \test_mem_fus
  attribute \src "scoreboard/test_mem_fu_matrix.py:72"
  wire width 8 input 0 \ld_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:73"
  wire width 8 input 1 \st_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:84"
  wire width 8 input 2 \req_rel_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:85"
  wire width 8 output 3 \loadable_o
  attribute \src "scoreboard/test_mem_fu_matrix.py:86"
  wire width 8 output 4 \storable_o
  attribute \src "scoreboard/test_mem_fu_matrix.py:75"
  wire width 8 input 5 \load_hit_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:76"
  wire width 8 input 6 \stwd_hit_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:88"
  wire width 8 input 7 \go_st_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:89"
  wire width 8 input 8 \go_ld_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:90"
  wire width 8 input 9 \go_die_i
  attribute \src "scoreboard/test_mem_fu_matrix.py:91"
  wire width 8 input 10 \req_rel_o
  attribute \src "scoreboard/test_mem_fu_matrix.py:92"
  wire width 8 input 11 \fn_issue_i
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 12 \clk
  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  wire width 1 input 13 \rst
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:51"
  wire width 8 \ldstdeps_ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:52"
  wire width 8 \ldstdeps_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:53"
  wire width 8 \ldstdeps_issue_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:56"
  wire width 8 \ldstdeps_load_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:58"
  wire width 8 \ldstdeps_stwd_hit_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:54"
  wire width 8 \ldstdeps_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:62"
  wire width 8 \ldstdeps_ld_hold_st_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:64"
  wire width 8 \ldstdeps_st_hold_ld_o
  cell \ldstdeps \ldstdeps
    connect \ld_pend_i \ldstdeps_ld_pend_i
    connect \st_pend_i \ldstdeps_st_pend_i
    connect \issue_i \ldstdeps_issue_i
    connect \load_hit_i \ldstdeps_load_hit_i
    connect \stwd_hit_i \ldstdeps_stwd_hit_i
    connect \go_die_i \ldstdeps_go_die_i
    connect \ld_hold_st_o \ldstdeps_ld_hold_st_o
    connect \st_hold_ld_o \ldstdeps_st_hold_ld_o
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:30"
  wire width 8 \fumemdeps_storable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:31"
  wire width 8 \fumemdeps_loadable_o
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:22"
  wire width 8 \fumemdeps_ld_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:21"
  wire width 8 \fumemdeps_st_pend_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:26"
  wire width 8 \fumemdeps_go_st_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:25"
  wire width 8 \fumemdeps_go_ld_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:27"
  wire width 8 \fumemdeps_go_die_i
  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:23"
  wire width 8 \fumemdeps_issue_i
  cell \fumemdeps \fumemdeps
    connect \storable_o \fumemdeps_storable_o
    connect \loadable_o \fumemdeps_loadable_o
    connect \ld_pend_i \fumemdeps_ld_pend_i
    connect \st_pend_i \fumemdeps_st_pend_i
    connect \go_st_i \fumemdeps_go_st_i
    connect \go_ld_i \fumemdeps_go_ld_i
    connect \go_die_i \fumemdeps_go_die_i
    connect \issue_i \fumemdeps_issue_i
    connect \rst \rst
    connect \clk \clk
  end
  process $group_0
    assign \ldstdeps_ld_pend_i 8'00000000
    assign \ldstdeps_ld_pend_i \ld_i
    sync init
  end
  process $group_1
    assign \ldstdeps_st_pend_i 8'00000000
    assign \ldstdeps_st_pend_i \st_i
    sync init
  end
  process $group_2
    assign \ldstdeps_issue_i 8'00000000
    assign \ldstdeps_issue_i \fn_issue_i
    sync init
  end
  process $group_3
    assign \ldstdeps_load_hit_i 8'00000000
    assign \ldstdeps_load_hit_i \load_hit_i
    sync init
  end
  process $group_4
    assign \ldstdeps_stwd_hit_i 8'00000000
    assign \ldstdeps_stwd_hit_i \stwd_hit_i
    sync init
  end
  process $group_5
    assign \ldstdeps_go_die_i 8'00000000
    assign \ldstdeps_go_die_i \go_die_i
    sync init
  end
  process $group_6
    assign \storable_o 8'00000000
    assign \storable_o \fumemdeps_storable_o
    sync init
  end
  process $group_7
    assign \loadable_o 8'00000000
    assign \loadable_o \fumemdeps_loadable_o
    sync init
  end
  process $group_8
    assign \fumemdeps_ld_pend_i 8'00000000
    assign \fumemdeps_ld_pend_i \ldstdeps_ld_hold_st_o
    sync init
  end
  process $group_9
    assign \fumemdeps_st_pend_i 8'00000000
    assign \fumemdeps_st_pend_i \ldstdeps_st_hold_ld_o
    sync init
  end
  process $group_10
    assign \fumemdeps_go_st_i 8'00000000
    assign \fumemdeps_go_st_i \stwd_hit_i
    sync init
  end
  process $group_11
    assign \fumemdeps_go_ld_i 8'00000000
    assign \fumemdeps_go_ld_i \load_hit_i
    sync init
  end
  process $group_12
    assign \fumemdeps_go_die_i 8'00000000
    assign \fumemdeps_go_die_i \go_die_i
    sync init
  end
  process $group_13
    assign \fumemdeps_issue_i 8'00000000
    assign \fumemdeps_issue_i \fn_issue_i
    sync init
  end
end