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Date: Fri, 22 May 2020 20:29:17 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Formal Verification
X-Bugzilla-Version: unspecified
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X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: lkcl@lkcl.net
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Message-ID: <bug-340-13-Ig9nXaXn72@https.bugs.libre-soc.org/>
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Subject: [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT
 pipeline needed
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