- m.d.submodules.perm_valid = perm_valid = PermissionValidator(113)
- m.d.sync += [
- Case(self.command, {
- # Search for PTE
- 1: [
- # Check first entry in set
- # TODO make module?
- read_port_l1.addr.eq(vma[0,2]),
- If(read_port_l1.data[0] == 1,
- perm_valid.data.eq(read_port_l1.data),
- perm_valid.xwr.eq(self.xwr),
- perm_valid.super.eq(self.super),
- perm_valid.super_access.eq(self.super_access),
- perm_valid.asid.eq(self.asid),
- self.valid,eq(perm_valid.valid)
- ),
- If(self.valid == 0,
- read_port_l1.addr.eq(vma[0,2] + 1),
- If(read_port_l1.data[0] == 1,
- perm_valid.data.eq(read_port_l1.data),
- perm_valid.xwr.eq(self.xwr),
- perm_valid.super.eq(self.super),
- perm_valid.super_access.eq(self.super_access),
- perm_valid.asid.eq(self.asid),
- self.valid,eq(perm_valid.valid)
- )
- )
- ]
- })
- ]
- return m
+ # Add submodules
+ # Submodules for L1 Cache
+ m.d.submodules.cam_L1 = self.cam_L1
+ m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port
+ m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.read_port
+ # Permission Validator Submodule
+ m.d.submodules.perm_valididator = self.perm_validator
+
+ # When MODE specifies translation
+ # TODO add in different bit length handling ie prefix 0s
+ with m.If(self.mode != 0):
+ m.d.comb += [
+ self.cam_L1.enable.eq(1)
+ ]
+ with m.Switch(self.command):
+ # Search
+ with m.Case("01"):
+ m.d.comb += [
+ write_L1.en.eq(0),
+ self.cam_L1.write_enable.eq(0),
+ self.cam_L1.data_in.eq(self.vma)
+ ]
+ # Write L1
+ # Expected that the miss will be handled in software
+ with m.Case("10"):
+ # Memory_L1 Logic
+ m.d.comb += [
+ write_L1.en.eq(1),
+ write_L1.addr.eq(self.address_L1),
+ # The first argument is the LSB
+ write_L1.data.eq(Cat(self.pte, self.asid))
+ ]
+ # CAM_L1 Logic
+ m.d.comb += [
+ self.cam_L1.write_enable.eq(1),
+ self.cam_L1.data_in.eq(self.vma),
+ ]
+ # TODO
+ #with m.Case("11"):