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Add test case for `riscv expose_custom`.
[riscv-tests.git]
/
debug
/
targets
/
RISC-V
/
spike-rtos.cfg
diff --git
a/debug/targets/RISC-V/spike-rtos.cfg
b/debug/targets/RISC-V/spike-rtos.cfg
index 159a70fac42c7ffcaa6af1f1371ef43f0f73fdce..e26ca8a43c4d8b37141ff05158fb8bc0239e5b2f 100644
(file)
--- a/
debug/targets/RISC-V/spike-rtos.cfg
+++ b/
debug/targets/RISC-V/spike-rtos.cfg
@@
-12,10
+12,12
@@
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
gdb_report_data_abort enable
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
gdb_report_data_abort enable
+gdb_report_register_access_error enable
# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
riscv expose_csrs 2288
# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
init
init