projects
/
riscv-tests.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Test FPRs that aren't XLEN in size.
[riscv-tests.git]
/
debug
/
targets
/
RISC-V
/
spike32.py
diff --git
a/debug/targets/RISC-V/spike32.py
b/debug/targets/RISC-V/spike32.py
index e80f60a07a51e6ae38ee0b2afad51f201e1f0146..dfcfc0134dc26a67dedbc1ee79fd4e0d3d1c38c2 100644
(file)
--- a/
debug/targets/RISC-V/spike32.py
+++ b/
debug/targets/RISC-V/spike32.py
@@
-6,12
+6,14
@@
class spike32_hart(targets.Hart):
ram = 0x10000000
ram_size = 0x10000000
instruction_hardware_breakpoint_count = 4
ram = 0x10000000
ram_size = 0x10000000
instruction_hardware_breakpoint_count = 4
- reset_vector
= 0x1000
- link_script_path = "spike
64
.lds"
+ reset_vector
s = [0x1000]
+ link_script_path = "spike
32
.lds"
class spike32(targets.Target):
harts = [spike32_hart()]
class spike32(targets.Target):
harts = [spike32_hart()]
- openocd_config_path = "spike.cfg"
+ openocd_config_path = "spike-1.cfg"
+ timeout_sec = 30
def create(self):
def create(self):
- return testlib.Spike(self)
+ # 64-bit FPRs on 32-bit target
+ return testlib.Spike(self, isa="RV32IMAFDC")