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Test FPRs that aren't XLEN in size.
[riscv-tests.git]
/
debug
/
targets
/
RISC-V
/
spike64.py
diff --git
a/debug/targets/RISC-V/spike64.py
b/debug/targets/RISC-V/spike64.py
index 84586e33f46d682d18ab63db92ec4b5c83562da5..2aa1dd057ef66a9723f76c201763658604b3b409 100644
(file)
--- a/
debug/targets/RISC-V/spike64.py
+++ b/
debug/targets/RISC-V/spike64.py
@@
-6,12
+6,14
@@
class spike64_hart(targets.Hart):
ram = 0x1212340000
ram_size = 0x10000000
instruction_hardware_breakpoint_count = 4
ram = 0x1212340000
ram_size = 0x10000000
instruction_hardware_breakpoint_count = 4
- reset_vector
= 0x1000
+ reset_vector
s = [0x1000]
link_script_path = "spike64.lds"
class spike64(targets.Target):
harts = [spike64_hart()]
link_script_path = "spike64.lds"
class spike64(targets.Target):
harts = [spike64_hart()]
- openocd_config_path = "spike.cfg"
+ openocd_config_path = "spike-1.cfg"
+ timeout_sec = 30
def create(self):
def create(self):
- return testlib.Spike(self)
+ # 32-bit FPRs only
+ return testlib.Spike(self, isa="RV64IMAFC")