-from nmigen import Signal, Cat, Const, Mux, Module, Array
-from nmigen.cli import verilog, rtlil
-from nmigen.hdl.rec import Record, Layout
-
-from collections.abc import Sequence
-
-
-class PrevControl:
- """ contains signals that come *from* the previous stage (both in and out)
- * i_valid: previous stage indicating all incoming data is valid.
- may be a multi-bit signal, where all bits are required
- to be asserted to indicate "valid".
- * o_ready: output to next stage indicating readiness to accept data
- * i_data : an input - added by the user of this class
- """
-
- def __init__(self, i_width=1):
- self.i_valid = Signal(i_width, name="p_i_valid") # prev >>in self
- self.o_ready = Signal(name="p_o_ready") # prev <<out self
-
- def connect_in(self, prev):
- """ helper function to connect stage to an input source. do not
- use to connect stage-to-stage!
- """
- return [self.i_valid.eq(prev.i_valid),
- prev.o_ready.eq(self.o_ready),
- eq(self.i_data, prev.i_data),
- ]
-
- def i_valid_logic(self):
- vlen = len(self.i_valid)
- if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
- all1s = Const(-1, (len(self.i_valid), False))
- return self.i_valid == all1s
- # single-bit i_valid case
- return self.i_valid
-
-
-class NextControl:
- """ contains the signals that go *to* the next stage (both in and out)
- * o_valid: output indicating to next stage that data is valid
- * i_ready: input from next stage indicating that it can accept data
- * o_data : an output - added by the user of this class
- """
- def __init__(self):
- self.o_valid = Signal(name="n_o_valid") # self out>> next
- self.i_ready = Signal(name="n_i_ready") # self <<in next
-
- def connect_to_next(self, nxt):
- """ helper function to connect to the next stage data/valid/ready.
- data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
- """
- return [nxt.i_valid.eq(self.o_valid),
- self.i_ready.eq(nxt.o_ready),
- eq(nxt.i_data, self.o_data),
- ]
-
- def connect_out(self, nxt):
- """ helper function to connect stage to an output source. do not
- use to connect stage-to-stage!
- """
- return [nxt.o_valid.eq(self.o_valid),
- self.i_ready.eq(nxt.i_ready),
- eq(nxt.o_data, self.o_data),
- ]
-
-
-def eq(o, i):
- """ makes signals equal: a helper routine which identifies if it is being
- passed a list (or tuple) of objects, or signals, or Records, and calls
- the objects' eq function.
-
- complex objects (classes) can be used: they must follow the
- convention of having an eq member function, which takes the
- responsibility of further calling eq and returning a list of
- eq assignments
-
- Record is a special (unusual, recursive) case, where the input may be
- specified as a dictionary (which may contain further dictionaries,
- recursively), where the field names of the dictionary must match
- the Record's field spec. Alternatively, an object with the same
- member names as the Record may be assigned: it does not have to
- *be* a Record.
- """
- if not isinstance(o, Sequence):
- o, i = [o], [i]
- res = []
- for (ao, ai) in zip(o, i):
- #print ("eq", ao, ai)
- if isinstance(ao, Record):
- for idx, (field_name, field_shape, _) in enumerate(ao.layout):
- if isinstance(field_shape, Layout):
- val = ai.fields
- else:
- val = ai
- if hasattr(val, field_name): # check for attribute
- val = getattr(val, field_name)
- else:
- val = val[field_name] # dictionary-style specification
- rres = eq(ao.fields[field_name], val)
- res += rres
- else:
- rres = ao.eq(ai)
- if not isinstance(rres, Sequence):
- rres = [rres]
- res += rres
- return res
-
-
-class StageChain:
- """ pass in a list of stages, and they will automatically be
- chained together via their input and output specs into a
- combinatorial chain.
-
- * input to this class will be the input of the first stage
- * output of first stage goes into input of second
- * output of second goes into input into third (etc. etc.)
- * the output of this class will be the output of the last stage
- """
- def __init__(self, chain):
- self.chain = chain
-
- def ispec(self):
- return self.chain[0].ispec()
-
- def ospec(self):
- return self.chain[-1].ospec()
-
- def setup(self, m, i):
- for (idx, c) in enumerate(self.chain):
- if hasattr(c, "setup"):
- c.setup(m, i) # stage may have some module stuff
- o = self.chain[idx].ospec() # only the last assignment survives
- m.d.comb += eq(o, c.process(i)) # process input into "o"
- if idx != len(self.chain)-1:
- ni = self.chain[idx+1].ispec() # becomes new input on next loop
- m.d.comb += eq(ni, o) # assign output to next input
- i = ni
- self.o = o # last loop is the output
-
- def process(self, i):
- return self.o
-
-
-class PipelineBase:
- """ Common functions for Pipeline API
- """
- def __init__(self, stage, in_multi=None, p_len=1, n_len=1):
- """ pass in a "stage" which may be either a static class or a class
- instance, which has four functions (one optional):
- * ispec: returns input signals according to the input specification
- * ispec: returns output signals to the output specification
- * process: takes an input instance and returns processed data
- * setup: performs any module linkage if the stage uses one.
-
- User must also:
- * add i_data member to PrevControl and
- * add o_data member to NextControl
- """
- self.stage = stage
-
- # set up input and output IO ACK (prev/next ready/valid)
- p = []
- n = []
- for i in range(p_len):
- p.append(PrevControl(in_multi))
- for i in range(n_len):
- n.append(NextControl())
- if p_len > 1:
- self.p = Array(p)
- else:
- self.p = p
- if n_len > 1:
- self.n = Array(n)
- else:
- self.n = n
-
- def connect_to_next(self, nxt, p_idx=0, n_idx=0):
- """ helper function to connect to the next stage data/valid/ready.
- """
- return self.n[n_idx].connect_to_next(nxt.p[p_idx])
-
- def connect_in(self, prev, idx=0, prev_idx=None):
- """ helper function to connect stage to an input source. do not
- use to connect stage-to-stage!
- """
- if prev_idx is None:
- return self.p[idx].connect_in(prev.p)
- return self.p[idx].connect_in(prev.p[prev_idx])
-
- def connect_out(self, nxt, idx=0, nxt_idx=None):
- """ helper function to connect stage to an output source. do not
- use to connect stage-to-stage!
- """
- if nxt_idx is None:
- return self.n[idx].connect_out(nxt.n)
- return self.n[idx].connect_out(nxt.n[nxt+idx])
-
- def set_input(self, i, idx=0):
- """ helper function to set the input data
- """
- return eq(self.p[idx].i_data, i)
-
- def ports(self):
- res = []
- for i in range(len(self.p)):
- res += [self.p[i].i_valid, self.p[i].o_ready,
- self.p[i].i_data]# XXX need flattening!]
- for i in range(len(self.n)):
- res += [self.n[i].i_ready, self.n[i].o_valid,
- self.n.o_data] # XXX need flattening!]
- return res
-
-
-class BufferedPipeline(PipelineBase):
- """ buffered pipeline stage. data and strobe signals travel in sync.
- if ever the input is ready and the output is not, processed data
- is stored in a temporary register.
-
- stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
- stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
- stage-1 p.i_data >>in stage n.o_data out>> stage+1
- | |
- process --->----^
- | |
- +-- r_data ->-+
-
- input data p.i_data is read (only), is processed and goes into an
- intermediate result store [process()]. this is updated combinatorially.
-
- in a non-stall condition, the intermediate result will go into the
- output (update_output). however if ever there is a stall, it goes
- into r_data instead [update_buffer()].
-
- when the non-stall condition is released, r_data is the first
- to be transferred to the output [flush_buffer()], and the stall
- condition cleared.
-
- on the next cycle (as long as stall is not raised again) the
- input may begin to be processed and transferred directly to output.
- """
-
- def __init__(self, stage, n_len=1, p_len=1, p_mux=None, n_mux=None):
- """ set up a BufferedPipeline (multi-input, multi-output)
- NOTE: n_len > 1 and p_len > 1 is NOT supported
-
- Arguments:
-
- * stage: see Stage API above
- * p_len: number of inputs (PrevControls + data)
- * n_len: number of outputs (NextControls + data)
- * p_mux: optional multiplex selector for incoming data
- * n_mux: optional multiplex router for outgoing data
- """
- PipelineBase.__init__(self, stage)
- self.p_mux = p_mux
- self.n_mux = n_mux
-
- # set up the input and output data
- for i in range(p_len):
- self.p[i].i_data = stage.ispec() # input type
- for i in range(n_len):
- self.n[i].o_data = stage.ospec()
-
- def elaborate(self, platform):
- m = Module()
-
- result = self.stage.ospec() # output data
-
- # need an array of buffer registers conforming to *output* spec
- r_data = []
- for i in range(len(self.p)):
- r = self.stage.ospec() # output type
- r_data.append(r)
- if hasattr(self.stage, "setup"):
- self.stage.setup(m, self.p[i].i_data)
- if len(r_data) > 1:
- r_data = Array(r_data)
-
- pi = 0 # TODO: use p_mux to decide which to select
- ni = 0 # TODO: use n_nux to decide which to select
-
- # establish some combinatorial temporaries
- o_n_validn = Signal(reset_less=True)
- i_p_valid_o_p_ready = Signal(reset_less=True)
- p_i_valid = Signal(reset_less=True)
- m.d.comb += [p_i_valid.eq(self.p[pi].i_valid_logic()),
- o_n_validn.eq(~self.n[ni].o_valid),
- i_p_valid_o_p_ready.eq(p_i_valid & self.p[pi].o_ready),
- ]
-
- # store result of processing in combinatorial temporary
- m.d.comb += eq(result, self.stage.process(self.p[pi].i_data))