-from nmigen import Signal, Cat, Const, Mux, Module
-from nmigen.cli import verilog, rtlil
-from collections.abc import Sequence
-
-
-class IOAckIn:
-
- def __init__(self):
- self.p_valid = Signal() # >>in - comes in from PREVIOUS stage
- self.n_ready = Signal() # in<< - comes in from the NEXT stage
-
-
-class IOAckOut:
-
- def __init__(self):
- self.n_valid = Signal() # out>> - goes out to the NEXT stage
- self.p_ready = Signal() # <<out - goes out to the PREVIOUS stage
-
-
-def eq(o, i):
- if not isinstance(o, Sequence):
- o, i = [o], [i]
- res = []
- for (ao, ai) in zip(o, i):
- res.append(ao.eq(ai))
- return res
-
-
-class BufferedPipeline:
- """ buffered pipeline stage. data and strobe signals travel in sync.
- if ever the input is ready and the output is not, processed data
- is stored in a temporary register.
-
- stage-1 i.p_valid >>in stage o.n_valid out>> stage+1
- stage-1 o.p_ready <<out stage i.n_ready <<in stage+1
- stage-1 i.data >>in stage o.data out>> stage+1
- | |
- process --->----^
- | |
- +-- r_data ->-+
-
- input data i_data is read (only), is processed and goes into an
- intermediate result store [process()]. this is updated combinatorially.
-
- in a non-stall condition, the intermediate result will go into the
- output (update_output). however if ever there is a stall, it goes
- into r_data instead [update_buffer()].
-
- when the non-stall condition is released, r_data is the first
- to be transferred to the output [flush_buffer()], and the stall
- condition cleared.
-
- on the next cycle (as long as stall is not raised again) the
- input may begin to be processed and transferred directly to output.
- """
- def __init__(self, stage):
- """ pass in a "stage" which may be either a static class or a class
- instance, which has three functions:
- * ispec: returns input signals according to the input specification
- * ispec: returns output signals to the output specification
- * process: takes an input instance and returns processed data
-
- i_data -> process() -> result --> o.data
- | ^
- | |
- +-> r_data -+
- """
- # input: strobe comes in from previous stage, ready comes in from next
- self.i = IOAckIn()
- #self.i.p_valid = Signal() # >>in - comes in from PREVIOUS stage
- #self.i.n_ready = Signal() # in<< - comes in from the NEXT stage
-
- # output: strobe goes out to next stage, ready comes in from previous
- self.o = IOAckOut()
- #self.o.n_valid = Signal() # out>> - goes out to the NEXT stage
- #self.o.p_ready = Signal() # <<out - goes out to the PREVIOUS stage
-
- # set up the input and output data
- self.i.data = stage.ispec() # input type
- self.r_data = stage.ospec() # all these are output type
- self.result = stage.ospec()
- self.o.data = stage.ospec()
- self.stage = stage
-
- def connect_next(self, nxt):
- """ helper function to connect the next stage data/valid/ready
- """
- return [nxt.i.p_valid.eq(self.o.n_valid),
- self.i.n_ready.eq(nxt.o.p_ready),
- eq(nxt.i.data, self.o.data),
- ]
-
- def connect_in(self, prev):
- """ helper function to connect stage to an input source. do not
- use to connect stage-to-stage!
- """
- return [self.i.p_valid.eq(prev.i.p_valid),
- prev.o.p_ready.eq(self.o.p_ready),
- eq(self.i.data, prev.i.data),
- ]
-
- def connect_out(self, nxt):
- """ helper function to connect stage to an output source. do not
- use to connect stage-to-stage!
- """
- return [nxt.o.n_valid.eq(self.o.n_valid),
- self.i.n_ready.eq(nxt.i.n_ready),
- eq(nxt.o.data, self.o.data),
- ]
-
- def set_input(self, i):
- """ helper function to set the input data
- """
- return eq(self.i.data, i)
-
- def update_buffer(self):
- """ copies the result into the intermediate register r_data,
- which will need to be outputted on a subsequent cycle
- prior to allowing "normal" operation.
- """
- return eq(self.r_data, self.result)
-
- def update_output(self):
- """ copies the (combinatorial) result into the output
- """
- return eq(self.o.data, self.result)
-
- def flush_buffer(self):
- """ copies the *intermediate* register r_data into the output
- """
- return eq(self.o.data, self.r_data)
-
- def ports(self):
- return [self.i.data, self.o.data]
-
- def elaborate(self, platform):
- m = Module()
-
- # establish some combinatorial temporaries
- o_n_validn = Signal(reset_less=True)
- i_p_valid_o_p_ready = Signal(reset_less=True)
- m.d.comb += [o_n_validn.eq(~self.o.n_valid),
- i_p_valid_o_p_ready.eq(self.i.p_valid & self.o.p_ready),
- ]