-from nmigen import Signal, Cat, Const, Mux, Module
-from nmigen.cli import verilog, rtlil
-from collections.abc import Sequence
-
-
-class PrevControl:
- """ contains signals that come *from* the previous stage (both in and out)
- * i_valid: input from previous stage indicating incoming data is valid
- * o_ready: output to next stage indicating readiness to accept data
- * i_data : an input - added by the user of this class
- """
-
- def __init__(self):
- self.i_valid = Signal(name="p_i_valid") # >>in
- self.o_ready = Signal(name="p_o_ready") # <<out
-
- def connect_in(self, prev):
- """ helper function to connect stage to an input source. do not
- use to connect stage-to-stage!
- """
- return [self.i_valid.eq(prev.i_valid),
- prev.o_ready.eq(self.o_ready),
- eq(self.data, prev.data),
- ]
-
-
-class NextControl:
- """ contains the signals that go *to* the next stage (both in and out)
- * o_valid: output indicating to next stage that data is valid
- * i_ready: input from next stage indicating that it can accept data
- * o_data : an output - added by the user of this class
- """
- def __init__(self):
- self.o_valid = Signal(name="n_o_valid") # out>>
- self.i_ready = Signal(name="n_i_ready") # <<in
-
- def connect_to_next(self, nxt):
- """ helper function to connect to the next stage data/valid/ready.
- data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
- """
- return [nxt.i_valid.eq(self.o_valid),
- self.i_ready.eq(nxt.o_ready),
- eq(nxt.data, self.data),
- ]
-
-
-def eq(o, i):
- if not isinstance(o, Sequence):
- o, i = [o], [i]
- res = []
- for (ao, ai) in zip(o, i):
- res.append(ao.eq(ai))
- return res
-
-
-class BufferedPipeline:
- """ buffered pipeline stage. data and strobe signals travel in sync.
- if ever the input is ready and the output is not, processed data
- is stored in a temporary register.
-
- stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
- stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
- stage-1 p.data >>in stage n.data out>> stage+1
- | |
- process --->----^
- | |
- +-- r_data ->-+
-
- input data p.data is read (only), is processed and goes into an
- intermediate result store [process()]. this is updated combinatorially.
-
- in a non-stall condition, the intermediate result will go into the
- output (update_output). however if ever there is a stall, it goes
- into r_data instead [update_buffer()].
-
- when the non-stall condition is released, r_data is the first
- to be transferred to the output [flush_buffer()], and the stall
- condition cleared.
-
- on the next cycle (as long as stall is not raised again) the
- input may begin to be processed and transferred directly to output.
- """
- def __init__(self, stage):
- """ pass in a "stage" which may be either a static class or a class
- instance, which has three functions:
- * ispec: returns input signals according to the input specification
- * ispec: returns output signals to the output specification
- * process: takes an input instance and returns processed data
-
- p.data -> process() -> result --> n.data
- | ^
- | |
- +-> r_data -+
- """
- self.stage = stage
-
- # set up input and output IO ACK (prev/next ready/valid)
- self.p = PrevControl()
- self.n = NextControl()
-
- # set up the input and output data
- self.p.data = stage.ispec() # input type
- self.r_data = stage.ospec() # all these are output type
- self.result = stage.ospec()
- self.n.data = stage.ospec()
-
- def connect_to_next(self, nxt):
- """ helper function to connect to the next stage data/valid/ready.
- data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
- """
- return self.n.connect_to_next(nxt.p)
-
- def connect_in(self, prev):
- """ helper function to connect stage to an input source. do not
- use to connect stage-to-stage!
- """
- return self.p.connect_in(prev.p)
-
- def connect_out(self, nxt):
- """ helper function to connect stage to an output source. do not
- use to connect stage-to-stage!
- """
- return [nxt.n.o_valid.eq(self.n.o_valid),
- self.n.i_ready.eq(nxt.n.i_ready),
- eq(nxt.n.data, self.n.data),
- ]
-
- def set_input(self, i):
- """ helper function to set the input data
- """
- return eq(self.p.data, i)
-
- def update_buffer(self):
- """ copies the result into the intermediate register r_data,
- which will need to be outputted on a subsequent cycle
- prior to allowing "normal" operation.
- """
- return eq(self.r_data, self.result)
-
- def update_output(self):
- """ copies the (combinatorial) result into the output
- """
- return eq(self.n.data, self.result)
-
- def flush_buffer(self):
- """ copies the *intermediate* register r_data into the output
- """
- return eq(self.n.data, self.r_data)
-
- def ports(self):
- return [self.p.data, self.n.data]
-
- def elaborate(self, platform):
- m = Module()
- if hasattr(self.stage, "setup"):
- self.stage.setup(m, self.p.data)
-
- # establish some combinatorial temporaries
- o_n_validn = Signal(reset_less=True)
- i_p_valid_o_p_ready = Signal(reset_less=True)
- m.d.comb += [o_n_validn.eq(~self.n.o_valid),
- i_p_valid_o_p_ready.eq(self.p.i_valid & self.p.o_ready),
- ]