- def __init__(self):
- # input: strobe comes in from previous stage, busy comes in from next
- #self.i_p_rst = Signal() # >>in - comes in from PREVIOUS stage
- self.i_p_stb = Signal() # >>in - comes in from PREVIOUS stage
- self.i_n_busy = Signal() # in<< - comes in from the NEXT stage
-
- # output: strobe goes out to next stage, busy comes in from previous
- self.o_n_stb = Signal() # out>> - goes out to the NEXT stage
- self.o_p_busy = Signal() # <<out - goes out to the PREVIOUS stage
-
- def elaborate(self, platform):
- m = Module()
-
- # establish some combinatorial temporaries
- o_p_busyn = Signal(reset_less=True)
- o_n_stbn = Signal(reset_less=True)
- i_n_busyn = Signal(reset_less=True)
- i_p_stb_o_p_busyn = Signal(reset_less=True)
- m.d.comb += [i_n_busyn.eq(~self.i_n_busy),
- o_n_stbn.eq(~self.o_n_stb),
- o_p_busyn.eq(~self.o_p_busy),
- i_p_stb_o_p_busyn.eq(self.i_p_stb & o_p_busyn),
- ]
-
- # store result of processing in combinatorial temporary
- with m.If(self.i_p_stb): # input is valid: process it
- m.d.comb += self.stage.process()
- # if not in stall condition, update the temporary register
- with m.If(o_p_busyn): # not stalled
- m.d.sync += self.stage.update_buffer()
-
- #with m.If(self.i_p_rst): # reset
- # m.d.sync += self.o_n_stb.eq(0)
- # m.d.sync += self.o_p_busy.eq(0)
- with m.If(i_n_busyn): # next stage is not busy
- with m.If(o_p_busyn): # not stalled
- # nothing in buffer: send (processed) input direct to output
- m.d.sync += [self.o_n_stb.eq(self.i_p_stb),
- self.stage.update_output(),
- ]
- with m.Else(): # o_p_busy is true, and something is in our buffer.
- # Flush the [already processed] buffer to the output port.
- m.d.sync += [self.o_n_stb.eq(1),
- self.stage.flush_buffer(),
- # clear stall condition, declare register empty.
- self.o_p_busy.eq(0),
- ]
- # ignore input, since o_p_busy is also true.
-
- # (i_n_busy) is true here: next stage is busy
- with m.Elif(o_n_stbn): # next stage being told "not busy"
- m.d.sync += [self.o_n_stb.eq(self.i_p_stb),
- self.o_p_busy.eq(0), # Keep the buffer empty
- # set the output data (from comb result)
- self.stage.update_output(),
- ]
- # (i_n_busy) and (o_n_stb) both true:
- with m.Elif(i_p_stb_o_p_busyn):
- # If next stage *is* busy, and not stalled yet, accept input
- m.d.sync += self.o_p_busy.eq(self.i_p_stb & self.o_n_stb)
-
- return m
-
- def ports(self):
- return [self.i_p_stb, self.i_n_busy,
- self.o_n_stb, self.o_p_busy,
- ]
-
-
-class BufPipe(BufferedPipeline, ExampleStage):