- def connect_out(self, nxt):
- """ helper function to connect stage to an output source. do not
- use to connect stage-to-stage!
- """
- return [nxt.o.n_valid.eq(self.o.n_valid),
- self.i.n_ready.eq(nxt.i.n_ready),
- eq(nxt.o.data, self.o.data),
- ]
-
- def set_input(self, i):
- """ helper function to set the input data
- """
- return eq(self.i.data, i)
-
- def update_buffer(self):
- """ copies the result into the intermediate register r_data,
- which will need to be outputted on a subsequent cycle
- prior to allowing "normal" operation.
- """
- return eq(self.r_data, self.result)
-
- def update_output(self):
- """ copies the (combinatorial) result into the output
- """
- return eq(self.o.data, self.result)
-
- def flush_buffer(self):
- """ copies the *intermediate* register r_data into the output
- """
- return eq(self.o.data, self.r_data)
-
- def ports(self):
- return [self.i.data, self.o.data]
-
- def elaborate(self, platform):
- m = Module()
-
- # establish some combinatorial temporaries
- o_n_validn = Signal(reset_less=True)
- i_p_valid_o_p_ready = Signal(reset_less=True)
- m.d.comb += [o_n_validn.eq(~self.o.n_valid),
- i_p_valid_o_p_ready.eq(self.i.p_valid & self.o.p_ready),
- ]
-
- # store result of processing in combinatorial temporary
- with m.If(self.i.p_valid): # input is valid: process it
- m.d.comb += eq(self.result, self.stage.process(self.i.data))
- # if not in stall condition, update the temporary register
- with m.If(self.o.p_ready): # not stalled
- m.d.sync += self.update_buffer()
-
- #with m.If(self.i.p_rst): # reset
- # m.d.sync += self.o.n_valid.eq(0)
- # m.d.sync += self.o.p_ready.eq(0)
- with m.If(self.i.n_ready): # next stage is ready
- with m.If(self.o.p_ready): # not stalled
- # nothing in buffer: send (processed) input direct to output
- m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
- self.update_output(),
- ]
- with m.Else(): # o.p_ready is false, and something is in buffer.
- # Flush the [already processed] buffer to the output port.
- m.d.sync += [self.o.n_valid.eq(1),
- self.flush_buffer(),
- # clear stall condition, declare register empty.
- self.o.p_ready.eq(1),
- ]
- # ignore input, since o.p_ready is also false.
-
- # (i.n_ready) is false here: next stage is ready
- with m.Elif(o_n_validn): # next stage being told "ready"
- m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
- self.o.p_ready.eq(1), # Keep the buffer empty
- # set the output data (from comb result)
- self.update_output(),
- ]
- # (i.n_ready) false and (o.n_valid) true:
- with m.Elif(i_p_valid_o_p_ready):
- # If next stage *is* ready, and not stalled yet, accept input
- m.d.sync += self.o.p_ready.eq(~(self.i.p_valid & self.o.n_valid))
-
- return m
-
- def ports(self):
- return [self.i.p_valid, self.i.n_ready,
- self.o.n_valid, self.o.p_ready,
- ]