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forgot to add submodules
[ieee754fpu.git]
/
src
/
add
/
fmul.py
diff --git
a/src/add/fmul.py
b/src/add/fmul.py
index 46ad8099874b28899484477e321a9b3171c56db1..130d49e814d05028f5248206c4e87611e304a35b 100644
(file)
--- a/
src/add/fmul.py
+++ b/
src/add/fmul.py
@@
-1,7
+1,7
@@
from nmigen import Module, Signal, Cat, Mux, Array, Const
from nmigen.cli import main, verilog
from nmigen import Module, Signal, Cat, Mux, Array, Const
from nmigen.cli import main, verilog
-from fpbase import FPNum, FPOp, Overflow, FPBase
+from fpbase import FPNum
In, FPNumOut
, FPOp, Overflow, FPBase
from nmigen_add_experiment import FPState
class FPMUL(FPBase):
from nmigen_add_experiment import FPState
class FPMUL(FPBase):
@@
-20,14
+20,18
@@
class FPMUL(FPBase):
m = Module()
# Latches
m = Module()
# Latches
- a = FPNum
(
self.width, False)
- b = FPNum
(
self.width, False)
- z = FPNum(self.width, False)
+ a = FPNum
In(None,
self.width, False)
+ b = FPNum
In(None,
self.width, False)
+ z = FPNum
Out
(self.width, False)
mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
product = Signal(mw)
of = Overflow()
mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
product = Signal(mw)
of = Overflow()
+ m.submodules.of = of
+ m.submodules.a = a
+ m.submodules.b = b
+ m.submodules.z = z
with m.FSM() as fsm:
with m.FSM() as fsm:
@@
-48,30
+52,30
@@
class FPMUL(FPBase):
with m.State("special_cases"):
#if a or b is NaN return NaN
with m.State("special_cases"):
#if a or b is NaN return NaN
- with m.If(a.is_nan
() | b.is_nan()
):
+ with m.If(a.is_nan
| b.is_nan
):
m.next = "put_z"
m.d.sync += z.nan(1)
#if a is inf return inf
m.next = "put_z"
m.d.sync += z.nan(1)
#if a is inf return inf
- with m.Elif(a.is_inf
()
):
+ with m.Elif(a.is_inf):
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
#if b is zero return NaN
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
#if b is zero return NaN
- with m.If(b.is_zero
()
):
+ with m.If(b.is_zero):
m.d.sync += z.nan(1)
#if b is inf return inf
m.d.sync += z.nan(1)
#if b is inf return inf
- with m.Elif(b.is_inf
()
):
+ with m.Elif(b.is_inf):
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
#if a is zero return NaN
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
#if a is zero return NaN
- with m.If(a.is_zero
()
):
+ with m.If(a.is_zero):
m.next = "put_z"
m.d.sync += z.nan(1)
#if a is zero return zero
m.next = "put_z"
m.d.sync += z.nan(1)
#if a is zero return zero
- with m.Elif(a.is_zero
()
):
+ with m.Elif(a.is_zero):
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
#if b is zero return zero
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
#if b is zero return zero
- with m.Elif(b.is_zero
()
):
+ with m.Elif(b.is_zero):
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
# Denormalised Number checks
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
# Denormalised Number checks
@@
-127,7
+131,8
@@
class FPMUL(FPBase):
# rounding stage
with m.State("round"):
# rounding stage
with m.State("round"):
- self.roundz(m, z, of, "corrections")
+ self.roundz(m, z, of.roundz)
+ m.next = "corrections"
# ******
# correction stage
# ******
# correction stage