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forgot to add submodules
[ieee754fpu.git]
/
src
/
add
/
fmul.py
diff --git
a/src/add/fmul.py
b/src/add/fmul.py
index 8ddd45eb8bda5eb5a18dd14feeb56fab6124f876..130d49e814d05028f5248206c4e87611e304a35b 100644
(file)
--- a/
src/add/fmul.py
+++ b/
src/add/fmul.py
@@
-28,6
+28,10
@@
class FPMUL(FPBase):
product = Signal(mw)
of = Overflow()
product = Signal(mw)
of = Overflow()
+ m.submodules.of = of
+ m.submodules.a = a
+ m.submodules.b = b
+ m.submodules.z = z
with m.FSM() as fsm:
with m.FSM() as fsm:
@@
-127,7
+131,7
@@
class FPMUL(FPBase):
# rounding stage
with m.State("round"):
# rounding stage
with m.State("round"):
- self.roundz(m, z, of)
+ self.roundz(m, z, of
.roundz
)
m.next = "corrections"
# ******
m.next = "corrections"
# ******