replace copy of FPState with import of FPState

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index d29d5404b552cdd6955c9bdfdf2ba25f95523fa1..46ad8099874b28899484477e321a9b3171c56db1 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,8 +1,8 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Cat, Mux, Array, Const

 from nmigen.cli import main, verilog
 
 from fpbase import FPNum, FPOp, Overflow, FPBase
 from nmigen.cli import main, verilog
 
 from fpbase import FPNum, FPOp, Overflow, FPBase

-
+from nmigen_add_experiment import FPState

 
 class FPMUL(FPBase):
 
 
 class FPMUL(FPBase):