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[ieee754fpu.git]
/
src
/
add
/
fpadd
/
statemachine.py
diff --git
a/src/add/fpadd/statemachine.py
b/src/add/fpadd/statemachine.py
index 2591a5807c0f924e12b69c080693689987193a1f..4418b3fa8f07471b5b9067a6175f0306ad10c5d8 100644
(file)
--- a/
src/add/fpadd/statemachine.py
+++ b/
src/add/fpadd/statemachine.py
@@
-32,13
+32,18
@@
from fpadd.addstages import FPAddAlignSingleAdd
class FPOpData:
def __init__(self, width, id_wid):
self.z = FPOpOut(width)
class FPOpData:
def __init__(self, width, id_wid):
self.z = FPOpOut(width)
+ self.z.data_o = Signal(width)
self.mid = Signal(id_wid, reset_less=True)
self.mid = Signal(id_wid, reset_less=True)
+ def __iter__(self):
+ yield self.z
+ yield self.mid
+
def eq(self, i):
return [self.z.eq(i.z), self.mid.eq(i.mid)]
def ports(self):
def eq(self, i):
return [self.z.eq(i.z), self.mid.eq(i.mid)]
def ports(self):
- return
[self.z, self.mid]
+ return
list(self)
class FPADDBaseMod:
class FPADDBaseMod:
@@
-202,13
+207,13
@@
class FPADDBase(FPState):
self.in_t.ack.eq(self.mod.in_t.ack),
self.o.mid.eq(self.mod.o.mid),
self.o.z.v.eq(self.mod.o.z.v),
self.in_t.ack.eq(self.mod.in_t.ack),
self.o.mid.eq(self.mod.o.mid),
self.o.z.v.eq(self.mod.o.z.v),
- self.o.z.
o_valid.eq(self.mod.o.z.o_valid
),
- self.mod.o.z.
i_ready.eq(self.o.z.i_ready
_test),
+ self.o.z.
valid_o.eq(self.mod.o.z.valid_o
),
+ self.mod.o.z.
ready_i.eq(self.o.z.ready_i
_test),
]
m.d.sync += self.add_stb.eq(add_stb)
m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
]
m.d.sync += self.add_stb.eq(add_stb)
m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
- m.d.sync += self.o.z.
i_ready
.eq(0) # likewise
+ m.d.sync += self.o.z.
ready_i
.eq(0) # likewise
#m.d.sync += self.in_t.stb.eq(0)
m.submodules.fpadd = self.mod
#m.d.sync += self.in_t.stb.eq(0)
m.submodules.fpadd = self.mod
@@
-230,7
+235,7
@@
class FPADDBase(FPState):
with m.Else():
m.d.sync += [self.add_ack.eq(0),
self.in_t.stb.eq(0),
with m.Else():
m.d.sync += [self.add_ack.eq(0),
self.in_t.stb.eq(0),
- self.o.z.
i_ready
.eq(1),
+ self.o.z.
ready_i
.eq(1),
]
with m.Else():
# done: acknowledge, and write out id and value
]
with m.Else():
# done: acknowledge, and write out id and value
@@
-290,6
+295,8
@@
class FPADD(FPID):
for i in range(rs_sz):
in_a = FPOpIn(width)
in_b = FPOpIn(width)
for i in range(rs_sz):
in_a = FPOpIn(width)
in_b = FPOpIn(width)
+ in_a.data_i = Signal(width)
+ in_b.data_i = Signal(width)
in_a.name = "in_a_%d" % i
in_b.name = "in_b_%d" % i
rs.append((in_a, in_b))
in_a.name = "in_a_%d" % i
in_b.name = "in_b_%d" % i
rs.append((in_a, in_b))
@@
-298,6
+305,7
@@
class FPADD(FPID):
res = []
for i in range(rs_sz):
out_z = FPOpOut(width)
res = []
for i in range(rs_sz):
out_z = FPOpOut(width)
+ out_z.data_o = Signal(width)
out_z.name = "out_z_%d" % i
res.append(out_z)
self.res = Array(res)
out_z.name = "out_z_%d" % i
res.append(out_z)
self.res = Array(res)
@@
-312,7
+320,7
@@
class FPADD(FPID):
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
- m.submodules += self.rs
+
#
m.submodules += self.rs
in_a = self.rs[0][0]
in_b = self.rs[0][1]
in_a = self.rs[0][0]
in_b = self.rs[0][1]